[SI-LIST] Re: How to simulate worse case eye

Scott, Al;

Thanks for sharing your thoughts. I in no way implied that obtaining an
accurate passive channel (the deterministic part) is a trivia job. I
strongly believe in the philosophy that you need to verify your model
for any simulation otherwise it's garbage in garbage out. In fact I
spent lots of time in the past few years try to do exactly what you
said, measure, correlate, measure, correlate, on PCB traces (dielectric
properties), vias, connectors, SMA launches and eventually full channel
correlation between measurement and simulation. We have made a lot of
progress in improving the quality of our models but still a lot to learn
from this point on.

As system vendor and often deal with PCB/system SI issue, our main focus
is to optimize our PCB/system design to work with intended chipset. Will
I bet my job on some screw-up of poor packaging/IC design ? No way --
that's pure gamble. Do I have time to sit down and measure/study every
single chip/packaging design to be used on my board BEFORE I see any
problems in the lab ? Not a chance either. With very limited time at
hand when running multiple projects in parallel, the only thing we can
do is to capture the major contributors and manage the rest following
best design practices. 

The original intent of my post is to try to understand the best approach
to deal with statistical side of the serdes link analysis, so that we
are not over pessimistic nor over optimistic in our channel design. The
assumption is that once we have a good handle on the major contributors
of channel performance (as you mentioned, loss, resonance, via/connector
crosstalk, skew etc.), what's next ? The natural step to me is to run
some eye diagram simulation and hopefully captured the worst case ISI
using the right pattern but not over design by using a pattern that have
0 probability of occurring in real life.

Cheers

Perry




======================================= 

Perry Qu 

IPD Design & Qualification, Alcatel-Lucent Canada Inc.

600 March Road, Ottawa ON, K2K 2E6, Canada 

DID: 613-7846720  Fax: 613-5993642 

Email: perry.qu@xxxxxxxxxxxxxxxxxx 

======================================= 


-----Original Message-----
From: Scott McMorrow [mailto:scott@xxxxxxxxxxxxx] 
Sent: Wednesday, March 11, 2009 1:30 PM
To: QU Perry
Cc: al.neves@xxxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: Re: [SI-LIST] Re: How to simulate worse case eye

Perry,

Here is Al and my response to your question.

There is no one in this world who can measure a full channel and include

all of the crosstalk components in each package, each package to PCB 
transition,  through via and cavity coupling, and across all of the 
connectors, vias and cavities in the path, crosstalk through antipad 
openings, and the complexities power system behavior on the transmitters

and receivers.  And, even if you were able to perform this monstrous 
measurement and create the largest sNp file in the world, you would 
still have no way to know if you've found the path with the worst case 
differential to common mode conversion due to laminate weave Er 
variation across one backplane system, let alone across an entire 
manufacturing line.

Our approach, therefore, is to use measurements to validate EM solvers, 
measurements to extract average material parameters, measurements to 
characterize Er variation across various laminates and weaves, EM 
solvers to develop worst case parametrics  that can be used in modeling,

and worst case models that can be used in simulation.  In addition, when

possible we like to characterize the drivers and receivers in the 
operational environment with proprietary  measurement techniques and 
stress patterns designed to allow us to understand and bound non-LTI and

stochastic behavior of the drivers and receivers.

When we are bought in on a project after the fact, it is because the 
system is broken.  We use measurements to correlate our solver models, 
and simulations to verify the aberrant behavior.  From this point we 
suggest solutions, usually based on signal-to-noise ratio 
considerations, and the reality of the particular system and installed
base.

When we are brought in on a fresh project before the design, we strive 
for near-optimal modeling and design techniques, using EM solvers, that 
take into account crosstalk from every possible source, realistic 
material properties across manufacturing variation and suppliers, and 
design methods to both characterize and mitigate worst case skew.  
Essentially we minimize phase velocity or group delay variation in the 
end-to-end channel, and design for one octave beyond what we are 
currently asked to design for(i.e. - 12 G design methods for a 6 G 
system specification.), since even DFE receivers cannot compensate for 
deterministic jitter due to frequency dependent propagation delay 
variation in the channel.  Generally the cost is in the upfront design 
itself, and not in the downstream manufacturing costs.  We strive for 
high signal-to-noise ratio and phase linear designs, and attack this 
vigorously at all possible points.

In our experience, most modern day channels break due to one of four 
things:  resonance, loss, skew, and noise. 

* Resonance is a gimmy.  It's been discussed ad infinitum and is easily 
solved with back drilling most of the time.  If your connector system 
resonates, you're usually SOL.

* Loss is also a gimmy with modern equalization.  By loss I mean the 
dielectric and conductor losses.  If the channel only had material loss,

it doesn't take DFE to reduce jitter.  Noise margin of the receiver is 
another matter.

* Skew is a huge issue.  It cannot be known without advanced material 
characterization and modeling.  If you think you have a handle on it, 
you probably don't .. and it cannot be compensated for without transmit 
or receive deskewing silicon, and a method to determine the individual 
differential skew of each channel.

* Noise is usually the largest reason we're brought in after the fact, 
and the rational for concentrating on signal-to-noise ratio.  Crosstalk 
is pervasive in most systems, and is often not modeled or characterized 
fully.  If you have an existing system that marketing wants to go 
faster, you have to measure-correlate, measure-correlate, 
measure-correlate, until you are sure your solvers and simulators have 
included everything. 

Remember, that unless you have a handle on all the deterministic noise 
components in a channel, it is not even useful to begin to analyze the 
truly random stochastic processes. And if you think you have a handle on

the linear, non-linear, deterministic and random processes within a 
transmitter, or at receiver input near it's threshold region, you 
probably don't.  And if you've lost those handles, then there is no way 
that any simulator can provide you with BER result that you can carry to

your bosses office and say ... "I bet my job on these results."


Best regards,

Scott and Al

-- 
Al Neves
Scott McMorrow
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
(401) 284-1827 Business
(401) 284-1840 Fax

http://www.teraspeed.com

Teraspeed(r) is the registered service mark of
Teraspeed Consulting Group LLC



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