[SI-LIST] Re: Flip Chip Solder Ball inductance
- From: Bi Han <mike_bihan@xxxxxxxxxxxx>
- To: "Raymond Y. Chen" <chen@xxxxxxxxxxx>
- Date: Fri, 23 Sep 2005 09:57:54 -0700 (PDT)
Raymond:
Thanks for the well elaborated explanation.
I found that I misused terminology "mutual inductance" and "self-inductance". I
always refer to partial self inductance and partial mutual inductance.
I used to think that partial self inductance is the loop inductance between
conductor and infinity faraway.
Also, I used to think that partial mutual inductance is the mutual inductance
between the loop, formed by conductor A and infinity-faraway, and the loop
formed by conductor B and infinity-faraway.
I guess my previous understanding is partly correct and partly wrong. There is
no real physical meaning of the loop formed by conductor and infinity-faraway.
Thanks for clarify one amateur SI fans' head.
Han
"Raymond Y. Chen" <chen@xxxxxxxxxxx> £º
Dear Han,
Based on any physics or EM text book, you will find the following definition
for inductance in the physical world:
1. Inductance L is magnetic flux through a loop area divided by the current.
2. Self Internal Inductance, due to the flux inside the conductor body,
approaches zero at higher frequencies because of the skin effect.
3. The remaining inductance is the Self External Inductance, due to the flux
outside the conductor body but within the loop area formed by the conductor,
commonly known as loop inductance.
4. Mutual inductance is the interaction between two loop areas.
From you message, it seems that you think self inductance is different than
the loop inductance. Actually, loop inductance is the self inductance
(L11=Lint + Lext). And self inductance value depends on the loop area, not
just the individual conductor size.
Unless you are talking about "Partial Self Inductance":
1. "Partial Inductance" is a mathematical representation and has no physical
meaning when comparing to loop inductance alone.
2. "Partial Inductances" are valid as long as they are defined in the
context of a loop. "Partial inductances" by themselves have no meaning.
But used in an inductance matrix, where they are combined with all "Partial
Self" and "Partial Mutual" inductances in a loop, the extracted values (not
unique) can be used to find unique voltages and currents within that loop.
You may find some more detailed information in the following slides:
http://www.eda.org/pub/ibis/summits/jun05/chen.pdf
Regards,
Raymond Y. Chen
Sigrity, Inc.
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx
> [mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Bi Han
> Sent: Tuesday, September 20, 2005 9:10 AM
> To: Aubrey_Sparkman@xxxxxxxx; weirsi@xxxxxxxxxx; si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: Flip Chip Solder Ball inductance
>
>
> Hi:
>
> Thanks for your all's message.
>
> I think solder ball and bonding wire will have their self
> inductance. As friends pointed out, loop inductance is more complicated.
>
> Below is my opinion on the impact from environment.
> If there is matching resistor (to gnd) on the IO pad, thus the
> loop inductance should be simply adding those bonding wires and
> vias. Those routing traces were matched and should not be counted
> into loop inductance.
>
> Loop is "Driver - Bonding - trace - Bonding - resistor - Bonding
> - REF plane -Bonding - back to Driver".
>
> If there is no matching resistor on the IO pad, then the routing
> trace will impact SI severely, its inductance should be added
> into loop inductance.
>
> Above is my personal view, I've not read related topics very
> extensively. So, maybe someone can make it more clear.
>
> thanks,
> Han
>
>
> Aubrey_Sparkman@xxxxxxxx wrote:
> Han,
> Inductance requires knowledge of the complete loop or an
> assumption of the complete current path. Where is the other solder ball?
>
> Aubrey Sparkman
> Enterprise Engineering Signal Integrity Team
> Dell, Inc.
> Aubrey_Sparkman@xxxxxxxx
> (512) 723-3592
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx
> [mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of Bi Han
> Sent: Tuesday, September 20, 2005 8:55 AM
> To: weirsi@xxxxxxxxxx; List` Si
> Subject: [SI-LIST] Re: Re: Flip Chip Solder Ball inductance
>
> I guess I could use VIA formula (5*H*ln(4h/d)) to estimate the
> inductance, since that applies to both via and bonding wire. It
> should works fine generally for bump.
>
> Steve: why you think it does not make sense?
>
> Maybe its inductance is too low so that trace parasitics start to
> dominate over.
>
> thanks,
> Han
>
>
> steve weir:
> Bi, the inductance of a single ball makes no real sense. If you
> do find=20 such a formula, be careful to identify the assumptions
> about the rest of=20 the path, and make sure that they also apply
> to your circumstances.
>
> Steve
> At 05:25 AM 9/20/2005 -0700, Bi Han wrote:
> >Hi:
> >
> >Is there any quick formula to estimate the solder ball inductance,
> >given=20 the geometric size, such as diameter/height.
> >
> >thanks,
> >Han
> >
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