[SI-LIST] Re: Flip Chip Solder Ball inductance
- From: Albert Ruehli <ruehli@xxxxxxxxxx>
- To: weirsi@xxxxxxxxxx
- Date: Fri, 23 Sep 2005 18:06:45 -0400
Hi Steve
I agree with your assessment. There is no replacement for learning the
basics. A
tool or technique can lead to wrong results if it is not well understood.
After a while
we develop a good understanding on how accurate the results are. PEEC
inductance
models can be very valuable and they give accurate results provided that
they are used
properly. As you say, one of the dangers is the inaccurate evaluation of
the partial
inductances especially for closely spaced conductor. I don't recommend
using the
Grover approximate equations for closely spaced conductors. However,
they are
useful for approximate calculations for people who do not have access to a
better
tool. Again, approximations can be very insightful.
Regards,
Al
Albert Ruehli
ruehli@xxxxxxxxxx
914-945-1592 TL 862-1592, Fax 914-945-4244
steve weir <weirsi@xxxxxxxxxx>
Sent by: si-list-bounce@xxxxxxxxxxxxx
09/23/2005 03:24 PM
Please respond to
weirsi
To
Albert Ruehli/Watson/IBM@IBMUS, mike_bihan@xxxxxxxxxxxx
cc
Aubrey_Sparkman@xxxxxxxx, "Raymond Y. Chen" <chen@xxxxxxxxxxx>,
si-list@xxxxxxxxxxxxx, si-list-bounce@xxxxxxxxxxxxx
Subject
[SI-LIST] Re: Flip Chip Solder Ball inductance
Albert, I guess whether one considers partial inductance useful, or
dangerous depends on what one's goals are. Used properly, partial
inductance can provide insights while saving a lot of redundant
calculations. Used improperly, partial inductance concepts lead to
grossly
wrong conclusions.
To my thinking, we start with the entire loop(s) and then break these down
with appropriate coupling coefficients. Then we can assign the
convenience
of partial inductances to various path segments. What I don't recommend
to
anyone is the notion of starting with a partial inductance of a segment
and
attempting to apply that within a path that is either not similar to, or
unknown with respect to the one that the partial inductance value was
derived from.
Regards,
Steve.
At 01:59 PM 9/23/2005 -0400, Albert Ruehli wrote:
>Hi
>once we learn to think in terms of partial inductances it becomes a very
>useful concept.
>Assuming that we have a rectangular loop, then its inductance (loop) is
>given by
>
>L(loop) = Lp_11 + Lp_22 + Lp_33 + Lp_44 - 2 Lp_13 - 2 Lp_24
>
>where Lp_ij are the partial inductances. Intuitively, we have the
>partial self inductances
>which have a flux associated with them to infinity. However for each of
>the partial self
>inductances, there is a partial mutual inductance associated to subtract
>the flux to infinity
>(from the other side) so that only the flux in the loop remains. So,
>partial inductances
>are very useful for inductance computations.
>
>Now assume that we have a solder ball and we know its partial self
>inductance. Is this
>number useful or not? So essentially we have Lp_11 and we don't exactly
>know where
>the return current is going to be. If the distance to the ground return
>is large compared
>to the length of the via, then the partial mutual inductance Lp_13 is
>relatively small
>and we can estimate the loop inductance as L(loop) as Lp_11 +
>Lp_33. If there
>are many ground returns, Lp_33 may be small. Also, we have assumed a
>quasi- 2D
>situation with respect to the top and bottom loop closure. However, the
>point I am
>trying to make is that the solder ball partial inductance can be a good
>rough estimate
>for the inductive discontinuity.
>
>Another point I want to make is that we don't need closed loops for
>partial inductances.
>We can make a PEEC model for a lambda/4 antenna where the end is open,
from a
>direct current path point of view. So the partial inductances of the
>antenna wires do
>not form a loop.
>
>Regards,
>Al
>Albert Ruehli
>ruehli@xxxxxxxxxx
>914-945-1592 TL 862-1592, Fax 914-945-4244
>
>
>
>
>Bi Han <mike_bihan@xxxxxxxxxxxx>
>Sent by: si-list-bounce@xxxxxxxxxxxxx
>
>09/23/2005 12:57 PM
>Please respond to
>mike_bihan
>
>To
>"Raymond Y. Chen" <chen@xxxxxxxxxxx>
>cc
>Aubrey_Sparkman@xxxxxxxx, weirsi@xxxxxxxxxx, si-list@xxxxxxxxxxxxx
>Subject
>[SI-LIST] Re: Flip Chip Solder Ball inductance
>
>
>
>
>Raymond:
>
>Thanks for the well elaborated explanation.
>
>I found that I misused terminology "mutual inductance" and
>"self-inductance". I always refer to partial self inductance and partial
>mutual inductance.
>
>I used to think that partial self inductance is the loop inductance
>between conductor and infinity faraway.
>Also, I used to think that partial mutual inductance is the mutual
>inductance between the loop, formed by conductor A and infinity-faraway,
>and the loop formed by conductor B and infinity-faraway.
>I guess my previous understanding is partly correct and partly wrong.
>There is no real physical meaning of the loop formed by conductor and
>infinity-faraway.
>
>Thanks for clarify one amateur SI fans' head.
>Han
>
>
>
>"Raymond Y. Chen" <chen@xxxxxxxxxxx> £º
>Dear Han,
>
>Based on any physics or EM text book, you will find the following
definition
>for inductance in the physical world:
>
>1. Inductance L is magnetic flux through a loop area divided by the
current.
>
>2. Self Internal Inductance, due to the flux inside the conductor body,
>approaches zero at higher frequencies because of the skin effect.
>
>3. The remaining inductance is the Self External Inductance, due to the
flux
>outside the conductor body but within the loop area formed by the
conductor,
>commonly known as loop inductance.
>
>4. Mutual inductance is the interaction between two loop areas.
>
> From you message, it seems that you think self inductance is different
than
>the loop inductance. Actually, loop inductance is the self inductance
>(L11=Lint + Lext). And self inductance value depends on the loop area,
not
>just the individual conductor size.
>
>Unless you are talking about "Partial Self Inductance":
>
>1. "Partial Inductance" is a mathematical representation and has no
physical
>meaning when comparing to loop inductance alone.
>
>2. "Partial Inductances" are valid as long as they are defined in the
>context of a loop. "Partial inductances" by themselves have no meaning.
>But used in an inductance matrix, where they are combined with all
"Partial
>Self" and "Partial Mutual" inductances in a loop, the extracted values
(not
>unique) can be used to find unique voltages and currents within that
loop.
>
>
>You may find some more detailed information in the following slides:
>http://www.eda.org/pub/ibis/summits/jun05/chen.pdf
>
>
>Regards,
>
>Raymond Y. Chen
>Sigrity, Inc.
>
>
>
> > -----Original Message-----
> > From: si-list-bounce@xxxxxxxxxxxxx
> > [mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Bi Han
> > Sent: Tuesday, September 20, 2005 9:10 AM
> > To: Aubrey_Sparkman@xxxxxxxx; weirsi@xxxxxxxxxx; si-list@xxxxxxxxxxxxx
> > Subject: [SI-LIST] Re: Flip Chip Solder Ball inductance
> >
> >
> > Hi:
> >
> > Thanks for your all's message.
> >
> > I think solder ball and bonding wire will have their self
> > inductance. As friends pointed out, loop inductance is more
complicated.
> >
> > Below is my opinion on the impact from environment.
> > If there is matching resistor (to gnd) on the IO pad, thus the
> > loop inductance should be simply adding those bonding wires and
> > vias. Those routing traces were matched and should not be counted
> > into loop inductance.
> >
> > Loop is "Driver - Bonding - trace - Bonding - resistor - Bonding
> > - REF plane -Bonding - back to Driver".
> >
> > If there is no matching resistor on the IO pad, then the routing
> > trace will impact SI severely, its inductance should be added
> > into loop inductance.
> >
> > Above is my personal view, I've not read related topics very
> > extensively. So, maybe someone can make it more clear.
> >
> > thanks,
> > Han
> >
> >
> > Aubrey_Sparkman@xxxxxxxx wrote:
> > Han,
> > Inductance requires knowledge of the complete loop or an
> > assumption of the complete current path. Where is the other solder
ball?
> >
> > Aubrey Sparkman
> > Enterprise Engineering Signal Integrity Team
> > Dell, Inc.
> > Aubrey_Sparkman@xxxxxxxx
> > (512) 723-3592
> >
> > -----Original Message-----
> > From: si-list-bounce@xxxxxxxxxxxxx
> > [mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of Bi Han
> > Sent: Tuesday, September 20, 2005 8:55 AM
> > To: weirsi@xxxxxxxxxx; List` Si
> > Subject: [SI-LIST] Re: Re: Flip Chip Solder Ball inductance
> >
> > I guess I could use VIA formula (5*H*ln(4h/d)) to estimate the
> > inductance, since that applies to both via and bonding wire. It
> > should works fine generally for bump.
> >
> > Steve: why you think it does not make sense?
> >
> > Maybe its inductance is too low so that trace parasitics start to
> > dominate over.
> >
> > thanks,
> > Han
> >
> >
> > steve weir:
> > Bi, the inductance of a single ball makes no real sense. If you
> > do find=20 such a formula, be careful to identify the assumptions
> > about the rest of=20 the path, and make sure that they also apply
> > to your circumstances.
> >
> > Steve
> > At 05:25 AM 9/20/2005 -0700, Bi Han wrote:
> > >Hi:
> > >
> > >Is there any quick formula to estimate the solder ball inductance,
> > >given=20 the geometric size, such as diameter/height.
> > >
> > >thanks,
> > >Han
> > >
>
>
>
>
>
>
>---------------------------------
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