Posts for si-list, 09-2005

Browse: Last Month: 08-2005 Main Archive Page Next Month: 10-2005

» [SI-LIST] Re: Cref, Vref and Vmeas in IBIS file -
» [SI-LIST] Re: Cref, Vref and Vmeas in IBIS file -
» [SI-LIST] Cref, Vref and Vmeas in IBIS file -
» [SI-LIST] Jitter Measurement Equipment and Techniques Net seminar. -
» [SI-LIST] Re: Length matching of DDR-1 data lines - does it really have to be that tight? -
» [SI-LIST] Re: questions for 2-layer PCB simulation -
» [SI-LIST] Re: Length matching of DDR-1 data lines - does it really have to be that tight? -
» [SI-LIST] Re: questions for 2-layer PCB simulation -
» [SI-LIST] Re: Length matching of DDR-1 data lines - does it really have to be that tight? -
» [SI-LIST] Re: Length matching of DDR-1 data lines - does it really have to be that tight? -
» [SI-LIST] Length matching of DDR-1 data lines - does it really have to be that tight? -
» [SI-LIST] Re: questions for 2-layer PCB simulation -
» [SI-LIST] Re: questions for 2-layer PCB simulation -
» [SI-LIST] Re: questions for 2-layer PCB simulation -
» [SI-LIST] Frequency dependent crosstalk coefficient -
» [SI-LIST] entry level engineeing positions -
» [SI-LIST] Re: regarding PCI-Express clocking scheme - dazzled & confused -
» [SI-LIST] 回信： questions for 2-layer PCB simulation -
» [SI-LIST] questions for 2-layer PCB simulation -
» [SI-LIST] Re: R: Re: R: LVDS Transmission Problem -
» [SI-LIST] R: Re: R: LVDS Transmission Problem -
» [SI-LIST] Re: R: LVDS Transmission Problem -
» [SI-LIST] Engineer and Technician openings at W.L. Gore & Associates, Inc. -
» [SI-LIST] Re: regarding PCI-Express clocking scheme - dazzled & confused -
» [SI-LIST] Re： Re: What can we get from solid ground plane? -
» [SI-LIST] Re: LVDS Transmission Problem -
» [SI-LIST] Re: LVDS Transmission Problem -
» [SI-LIST] R: LVDS Transmission Problem -
» [SI-LIST] LVDS Transmission Problem -
» [SI-LIST] regarding PCI-Express clocking scheme - dazzled & confused -
» [SI-LIST] Re: What can we get from solid ground plane? -
» [SI-LIST] Re: What can we get from solid ground plane? -
» [SI-LIST] Re: What can we get from solid ground plane? -
» [SI-LIST] Re: si post-process tool for sharing -
» [SI-LIST] Re: si post-process tool for sharing -
» [SI-LIST] Continue on the topic of partial inductance. -
» [SI-LIST] How does HFSS model capacitors -
» [SI-LIST] Re: What can we get from solid ground plane? -
» [SI-LIST] Re: What can we get from solid ground plane? -
» [SI-LIST] What can we get from solid ground plane? -
» [SI-LIST] Re: Flip Chip Solder Ball inductance -
» [SI-LIST] Re: Flip Chip Solder Ball inductance -
» [SI-LIST] Re: Flip Chip Solder Ball inductance -
» [SI-LIST] si post-process tool for sharing -
» [SI-LIST] Re: Flip Chip Solder Ball inductance -
» [SI-LIST] Re: PCB Trace Antenna -
» [SI-LIST] Partial Inductance -
» [SI-LIST] Re: Electrical length -
» [SI-LIST] PCB Trace Antenna -
» [SI-LIST] Re: Flip Chip Solder Ball inductance -
» [SI-LIST] Re: Electrical length -
» [SI-LIST] Re: XGMII interfaces -
» [SI-LIST] XGMII interfaces -
» [SI-LIST] Electrical length -
» [SI-LIST] Re: Flip Chip Solder Ball inductance -
» [SI-LIST] OT: RoHS -
» [SI-LIST] test -
» [SI-LIST] Re: :PCB Trace Antenna -
» [SI-LIST] PCB Trace Antenna -
» [SI-LIST] Re: :PCB Trace Antenna -
» [SI-LIST] Re: :PCB Trace Antenna -
» [SI-LIST] Re: PCB Trace Antenna -
» [SI-LIST] Re: PCB Trace Antenna -
» [SI-LIST] Re: PCB Trace Antenna -
» [SI-LIST] Re: PCB Trace Antenna -
» [SI-LIST] Re: PCB Trace Antenna -
» [SI-LIST] PCB Trace Antenna -
» [SI-LIST] DDR2 buffer model -
» [SI-LIST] Re: IBIS model for Lattice FPGA XP failed icx parse. -
» [SI-LIST] IBIS model for Lattice FPGA XP failed icx parse. -
» [SI-LIST] Re: IBIS creation -
» [SI-LIST] Re: Re： [SI-LIST] Re: Flip Chip Solder Ball i nd uctance -
» [SI-LIST] Re: Clock jitter -
» [SI-LIST] Recall: Re: Clock jitter -
» [SI-LIST] Re: Clock jitter -
» [SI-LIST] Re: Clock jitter -
» [SI-LIST] Re: Flip Chip Solder Ball inductance -
» [SI-LIST] R: Flip Chip Solder Ball inductance -
» [SI-LIST] Re: Flip Chip Solder Ball inductance -
» [SI-LIST] Re： Re: Flip Chip Solder Ball inductance -
» [SI-LIST] Re: Flip Chip Solder Ball inductance -
» [SI-LIST] Flip Chip Solder Ball inductance -
» [SI-LIST] Poll- IBIS Creation -
» [SI-LIST] Looking for few good Allegro men -
» [SI-LIST] Re: Clock jitter -
» [SI-LIST] Re: Clock jitter -
» [SI-LIST] Re: Clock jitter -
» [SI-LIST] Re: Clock jitter -
» [SI-LIST] Re: Clock jitter -
» [SI-LIST] Re: Clock jitter -
» [SI-LIST] Clock jitter -
» [SI-LIST] IBIS Modeling Cookbook for Version 4.0 available! -
» [SI-LIST] IBIS model for CY22393 -
» [SI-LIST] IBIS -
» [SI-LIST] can a bus hold circuit amplify crosstalk? -
» [SI-LIST] Job Openings at Maxtor -
» [SI-LIST] package design job -
» [SI-LIST] Asian IBIS Summit Second Announcement -
» [SI-LIST] Re: About W-element formats -
» [SI-LIST] Mixed Signal Design Tools Workshop at Georgia Tech -
» [SI-LIST] Re: About W-element formats -
» [SI-LIST] Re: Analog and Digital grounds -
» [SI-LIST] Re: Analog and Digital grounds -
» [SI-LIST] About W-element formats -
» [SI-LIST] Re: Analog and Digital grounds -
» [SI-LIST] Re: Analog and Digital grounds -
» [SI-LIST] Analog and Digital grounds -
» [SI-LIST] Re: when is a PE license required? -
» [SI-LIST] when is a PE license required? -
» [SI-LIST] Re: Why should we tie AGND and DGND -
» [SI-LIST] Re: Why should we tie AGND and DGND -
» [SI-LIST] 2006 EMC Symposium in Singapore -
» [SI-LIST] Re: IBIS creation -
» [SI-LIST] Why should we tie AGND and DGND -
» [SI-LIST] Re: IBIS creation -
» [SI-LIST] IBIS creation -
» [SI-LIST] September 13, 2005 IEEE-EMC Santa Clara Valley Chapter Social meeting -
» [SI-LIST] Re: Stackup Suggestion for E1 transportor card -
» [SI-LIST] New Semiconductor Technology -
» [SI-LIST] Stackup Suggestion for E1 transportor card -
» [SI-LIST] How to extract spice netlist from cadence BLD file? -
» [SI-LIST] Re: Looking for IBIS model for any DDR2 SODIMM Module? -
» [SI-LIST] Re: Looking for IBIS model for any DDR2 SODIMM Module? -
» [SI-LIST] Looking for IBIS model for any DDR2 SODIMM Module? -
» [SI-LIST] Emissions radiated from Quartz Crystal -
» [SI-LIST] Effects of number of windings on ferrite core -
» [SI-LIST] Signal Integrity opening at Enterasys Networks -
» [SI-LIST] Analog, "characterization" project -
» [SI-LIST] Re: Guidlines regarding the CE Certification for a Product -
» [SI-LIST] DDR 2 Unbuffered DIMM - differential clock termination -
» [SI-LIST] Contractor needed, Intel Oregon -
» [SI-LIST] Re: EMI optimized CPLD/FPGA -
» [SI-LIST] Re: EMI optimized CPLD/FPGA -
» [SI-LIST] EMI optimized CPLD/FPGA -
» [SI-LIST] dielectric conductance effect on rise time -
» [SI-LIST] Modeling and measurement of Connector -
» [SI-LIST] Re: Guidlines regarding the CE Certification for a Product -
» [SI-LIST] Guidlines regarding the CE Certification for a Product -
» [SI-LIST] Re: Differential Z-One port -
» [SI-LIST] Re: BUS TRANSLATION USING RESISTORS ONLY -
» [SI-LIST] BUS TRANSLATION USING RESISTORS ONLY -
» [SI-LIST] Re: VME connector models -
» [SI-LIST] Diff Z-One port -
» [SI-LIST] Re: Differential Z-One port -
» [SI-LIST] Re: Differential Z-One port -
» [SI-LIST] Differential Z-One port -
» [SI-LIST] Mixed Signal Design Tools Workshop -
» [SI-LIST] Re: A doubt in PADS 2005 -
» [SI-LIST] AW: VME connector models -
» [SI-LIST] Re: A doubt in PADS 2005 -
» [SI-LIST] Re: VME connector models -
» [SI-LIST] Re: VME connector models -
» [SI-LIST] Re: 50 Ohm vs 75 ohm -