[SI-LIST] Re: Flight time measurements and post-route analysis
- From: "Hassan O. Ali" <hassan@xxxxxxxx>
- To: "Si-List@Freelists. Org" <si-list@xxxxxxxxxxxxx>
- Date: Thu, 31 Jan 2002 14:25:29 -0500
Todd Westerhoff wrote:
>
> Question for the group:
>
> Most commercial SI tools seem to measure flight times to the receiver's
> input thresholds. Thus, for a given transition, they report a "min" and
> "max" flight time based on the threshold settings.
The tools say they measure flight times to Vih/Vil, but it's a different
thing what they actually do! In SPECCTRAQuest, for example, I always
have to set my own custom measurements to get it right!
Now, you ask:
1. Should F/T be measured to Vih/Vil?
2. Should F/T be measured to some other voltage reference?
My answer: I do both!
The intent is always to close the "loop"! If the receiver timing data is
referenced to Vih/Vil, I measure F/T to Vih/Vil thresholds. If the
timing data is referenced to any other voltage threshold, I measure F/T
to that voltage threshold. In this way, I get a complete timing loop
with no gaps and no overlaps:
driver Tco (time to Vmeas) + flight time (time from driver Vmeas to
receiver Vthreshold) + receiver setup time (time from Vthreshold to when
data is considered valid)
Min and Max F/T numbers are determined by driver/receiver corners
(fast/slow), transmission line corners (min/max length, fast/slow prop.
velocity).
Now, the Tco number specified in the data sheets is with reference to a
certain reference load. I only correct the buffer delay numbers if:
1. I've a marginal timing performance
2. the numbers make my worstcase worse!
Let me start with the second case. I want my worst case to be an
absolute worst case, because if the interface works in an absolute worst
case without too much sacrifice, then there is nothing else to wish for!
If by correcting for the buffer delay it buys me some picoseconds
(positive margin) then I don't care. But if I find out that I loose some
picoseconds when I correct for the buffer delay (i.e. it makes my
worstcase worse), then I go for it so that I have an absolute worst
case.
When my timing performance is marginal (say with +/- 10ps margin), I
make buffer delay corrections to make my timing calculations more
accurate. That (from my experience) usually buys more time into the
timing margin.
Regards.
Hassan.
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