[SI-LIST] Re: Flight time measurements and post-route analysis
- From: "Abe Riazi" <ARIAZI@xxxxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Sun, 10 Feb 2002 08:27:45 -0800
Todd Westerhoff Wrote:
>
> Most commercial SI tools seem to measure flight times to the receiver's
> input thresholds. Thus, for a given transition, they report a "min" and
> "max" flight time based on the threshold settings.
>
.
.
>
> My question is: what techniques are people predominantly using: the
Vil/Vih
> method, the reference voltage, or something in-between?
>
Dear Todd and others:
I have also thought about ways of measuring flight times
and concluded that the Vil/Vih method is preferable in many
applications.
When using XTK, I have explored two techniques for determining flight times
of single ended and differential signals.
One approach utilizes the driver to receiver network delays outputted
by XNS in the Report (.rep), Interconnect Delay Data (.idd ) or
General Report (.gen) files. However, the .rep results need to be examined
for asterisk ( * ), as delay fields followed by asterisk indicate
possible errors and can be unreliable.
Another method is to measure delays on XNS Waveviewer window.
The cursor can be used to ascertain the min/max rise and fall delays
from intersection points of the rising and falling edges of the waveform
and the receiver's low/high logic thresholds.
Above procedurres are applicable to pre-route, post-route, single board and
multi-board designs although, effects of TIME_TO_VM must be taken
into consideration when appraising results of these methods.
With V(m) correction Enabled, XNS will subtract driver TIME_TO_VM
and report (in .idd, .rep, or .gen) the corrected delays. Subsequently,
the values given in XNS report files can differ from those measured with
the cursor. Furthermore, TIME_TO_VM correction (to prevent double
counting of buffer intrinsic delay) can be essential when flight time values
are intended for setup/hold timing margin computations.
Logic thresholds influence the min/max propagation delay values. An IBIS
model's logic low ( Vil ) and high ( Vih ) appear (after executing IBIS2XTK)
as THRS: statements in Quad models. Verifying correctness of receiver
thresholds is a good practice, particularly for devices having multiple
thresholds such as SSTL logic with Vil (ac), Vil(dc), Vih(dc) and Vih(ac).
The XNS simulation period (e.g. reciprocal of frequency) needs to be
selected correctly. Please note that the data, address and
control signals may switch at frequencies different from that
of bus clock. For instance, when bus clock frequency is 100 MHz
the data signals may operate at maximum frequency of 200 MHz
(e.g. 2X interface). Therefore, in this example the optimum XNS
period is 5nS (rather than 10nS) when simulating the data lines
(The optimum simulation frequencies for various signals are often
derived from the bus "timing diagrams"). A small XNS period
may lead to a simulation where the flight time exceeds one half
of period. It is then necessary that XNS option
"Time of Flight for Delay" be Enable, in order to produce accurate
timing results.
I hope you find this information helpful.
Best Regards,
Abe Riazi
ServerWorks
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