[SI-LIST] Re: Effect of Pwr-Gnd plane pairing vs. non-paired planes on signal return currents
- From: "Perry Qu" <perry.qu@xxxxxxxxxxx>
- To: <alexh1@xxxxxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Thu, 16 Feb 2006 16:26:00 -0500
Alex:
You got some good response on this. Just want to point out that for the
first stackup, you need to be careful about what to put on those internal
signals layers referencing power planes, e.g., you don't want to put 3.3V
I/O signals next to 1.2V plane. This adds complexity to your routing rules.
Regards
Perry
=======================================
Perry Qu
Design & Qualification, Alcatel Canada
600 March Road, Ottawa ON, K2K 2E6
DID: 613-7846720 Fax: 613-5993642
Email: perry.qu@xxxxxxxxxxx
=======================================
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Alex Horvath
Sent: Thursday, February 16, 2006 2:45 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Effect of Pwr-Gnd plane pairing vs. non-paired planes on
signal return currents
Normally, when I design a multi layer stackup I always try to alternate and
pair Pwr-Gnd planes to maximize inter-plane capacitance. For example, a 16
layer stackup might look like-
Sig - - - - - - -
Gnd --------------
Pwr --------------
Sig - - - - - - - -
Sig - - - - - - - -
Gnd --------------
Pwr --------------
Sig - - - - - - - -
Sig - - - - - - - -
Gnd --------------
Pwr --------------
Sig - - - - - - - -
Sig - - - - - - - -
Gnd---------------
Pwr ---------------
Sig - - - - - - -
For cost reasons I might be forced into a stackup with the same number of
signal layers but with 2 power planes removed (14 layers, same dielectric
thickness) -
Sig - - - - - - -
Gnd --------------
Pwr --------------
Sig - - - - - - - -
Sig - - - - - - - -
Gnd --------------
Sig - - - - - - - -
Sig - - - - - - - -
Gnd --------------
Sig - - - - - - - -
Sig - - - - - - - -
Gnd---------------
Pwr ---------------
Sig - - - - - - -
Let's assume a signal traverses from the top signal layer to the bottom
layer in both stackups. Let us also assume as a worst case that there are no
nearby vias or decoup caps and the signal edge rate is approximately 10
times the via length (about 200 psec). Is there a significant difference in
the expected signal quality when comparing these 2 stackups?
My gut feel is that all else being equal the primary factor determining
signal quality is the spacing of the planes. The DC assignment of the planes
has (again ignoring effect of gnd or pwr vias) little effect and thus the
signal quality in the above cases would be virtually identical.
Since I hate to bet my designs on a gut feel hopefully someone can confirm
or deny my assumptions.
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