[SI-LIST] Re: Effect of Pwr-Gnd plane pairing vs. non-paired planes on signal return currents

  • From: "George Peterson" <George_Peterson@xxxxxxxxx>
  • To: Aubrey_Sparkman@xxxxxxxx, vinu@xxxxxxxxx
  • Date: Thu, 16 Feb 2006 17:13:54 -0500

Alex, Aubrey,

I also made the assumption that the question was initially past the PWR
to GND reference transition
issue. Whatever the case may be, I agree that this is the dominant
affect.=20

I read the question to ask what effect the plane-to-plane capacitance
has in helping a reference current
"jump" to where it needs to be. If we assume at least 15 mils of
dielectric between the planes surrounding
the inner signal layers, and also that there will be significant signal
routing on these layers, then I don't
see plane-to-plane capacitance a top to bottom transition.

It seems to me that the ref current mechanisms in both systems would be
very similar...even if the
edge rate was much faster.

George Peterson
Sr. Signal Integrity Engineer
Jabil Circuit, Inc.
(727) 803-3743
george_peterson@xxxxxxxxx



-----Original Message-----
From: Aubrey_Sparkman@xxxxxxxx [mailto:Aubrey_Sparkman@xxxxxxxx]=20
Sent: Thursday, February 16, 2006 3:51 PM
To: George Peterson; vinu@xxxxxxxxx
Cc: alexh1@xxxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: RE: [SI-LIST] Re: Effect of Pwr-Gnd plane pairing vs.
non-paired planes on signal return currents

George,
Looks like you made an assumption about my premise....=20

Aubrey Sparkman=20
Enterprise Engineering Signal Integrity Team
Dell, Inc.=20
Aubrey_Sparkman@xxxxxxxx=20
(512) 723-3592

-----Original Message-----
From: George Peterson [mailto:George_Peterson@xxxxxxxxx]=20
Sent: Thursday, February 16, 2006 2:41 PM
To: Sparkman, Aubrey; vinu@xxxxxxxxx
Cc: alexh1@xxxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: RE: [SI-LIST] Re: Effect of Pwr-Gnd plane pairing vs.
non-paired planes on signal return currents

Aubrey,

Look again, your original premise is wrong. Top to bottom is a PWR to
GND transition on both stackups.

George Peterson
Sr. Signal Integrity Engineer
Jabil Circuit, Inc.
(727) 803-3743
george_peterson@xxxxxxxxx



-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Aubrey_Sparkman@xxxxxxxx
Sent: Thursday, February 16, 2006 3:29 PM
To: vinu@xxxxxxxxx
Cc: alexh1@xxxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Effect of Pwr-Gnd plane pairing vs. non-paired
planes on signal return currents

Vinu,
I don't disagree; my point was a hint that I didn't think Alex was
asking about the biggest performance limiting feature.


Aubrey Sparkman=3D20
Enterprise Engineering Signal Integrity Team Dell, Inc.=3D20
Aubrey_Sparkman@xxxxxxxx=3D20
(512) 723-3592

-----Original Message-----
From: Vinu Arumugham [mailto:vinu@xxxxxxxxx]=3D20
Sent: Thursday, February 16, 2006 2:20 PM
To: Sparkman, Aubrey
Cc: alexh1@xxxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: Re: [SI-LIST] Re: Effect of Pwr-Gnd plane pairing vs.
non-paired planes on signal return currents

If there are no ground vias nearby, a ground reference to ground
reference switch would behave the same as a ground reference to a power
reference switch.

I expect the two stack-ups to behave the same.

Thanks,
Vinu

Aubrey_Sparkman@xxxxxxxx wrote:

>Alex,
>The thing that caught my attention is that your signal switched =
from=3D20

>ground reference on top to power referenced on bottom, not that =
you=3D20=20
>removed a couple of reference planes....=3D3D20
>
>But that's just my quick gut reaction....
>
>Aubrey Sparkman=3D3D20
>Enterprise Engineering Signal Integrity Team Dell, Inc.=3D3D20=3D20=20
>Aubrey_Sparkman@xxxxxxxx=3D3D20
>(512) 723-3592
>
>-----Original Message-----
>From: si-list-bounce@xxxxxxxxxxxxx=3D20
>[mailto:si-list-bounce@xxxxxxxxxxxxx]
>On Behalf Of Alex Horvath
>Sent: Thursday, February 16, 2006 1:45 PM
>To: si-list@xxxxxxxxxxxxx
>Subject: [SI-LIST] Effect of Pwr-Gnd plane pairing vs. non-paired=3D20=20
>planes on signal return currents
>
>Normally, when I design a multi layer stackup I always try to alternate

>and pair Pwr-Gnd planes to maximize inter-plane capacitance. For=3D20=20
>example, a 16 layer stackup might look like-
>  =3D3D20
>  =3D3D20
>  Sig    - - - - - - -=3D3D20
>  Gnd  --------------
>  Pwr  --------------
>  Sig  - - - - - - - -
>  Sig  - - - - - - - -
>  Gnd  --------------
>  Pwr  --------------
>  Sig  - - - - - - - -
>  Sig  - - - - - - - -
>  Gnd  --------------
>  Pwr  --------------
>  Sig  - - - - - - - -
>  Sig  - - - - - - - -
>  Gnd---------------
>  Pwr ---------------
>  Sig  - - - - - - -=3D3D20
>  =3D3D20
>  For cost reasons I might be forced into a stackup with the same=3D20=20
>number of signal layers but with 2 power planes removed (14 =
layers,=3D20=20
>same dielectric thickness) -
>  =3D3D20
>  Sig    - - - - - - -=3D3D20
>  Gnd  --------------
>  Pwr  --------------
>  Sig  - - - - - - - -
>  Sig  - - - - - - - -
>  Gnd  --------------
>  Sig  - - - - - - - -
>  Sig  - - - - - - - -
>  Gnd  --------------
>  Sig  - - - - - - - -
>  Sig  - - - - - - - -
>  Gnd---------------
>  Pwr ---------------
>  Sig  - - - - - - -=3D3D20
>  =3D3D20
>  =3D3D20
>  Let's assume a signal traverses from the top signal layer to the=3D20 =

>bottom layer in both stackups. Let us also assume as a worst case
that=3D20
>there are no nearby vias or decoup caps and the signal edge rate =
is=3D20=20
>approximately 10 times the via length (about 200 psec). Is there a=3D20 =

>significant difference in the expected signal quality when =
comparing=3D20

>these 2 stackups?
>  =3D3D20
>  My gut feel is that all else being equal the primary factor=3D20=20
>determining signal quality is the spacing of the planes. The DC=3D20=20
>assignment of the planes has (again ignoring effect of gnd or pwr vias)

>little effect and thus the signal quality in the above cases would
be=3D20
>virtually identical.
>  =3D3D20
>  Since I hate to bet my designs on a gut feel hopefully someone =
can=3D20

>confirm or deny my assumptions.
>  =3D3D20
>
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