[SI-LIST] Re: Decoupling Capacitor ESR/ESL
- From: "Lee Ritchey" <leeritchey@xxxxxxxxxxxxx>
- To: "Steve Weir" <weirsi@xxxxxxxxxx>, "Erin.McPhalen@xxxxxxxxxxxxxxxxxxxxxxxxx" <Erin.McPhalen@xxxxxxxxxxxxxxxxxxxxxxxxx>, si-list@xxxxxxxxxxxxx
- Date: Wed, 28 Jun 2006 18:24:51 -0700
It's the pesky Z axis agiain. Sadly, it is always with us in PCBs and,
yep, it dominates the problem for nearly all of us. Once in a while, we
can make a configuration where it isn't dominant, such as a multilayer BGA
package, then everything gets better. No question, it can be shown that
there are configurations where the benefit of ultra low inductance
capacitors such as IDCs or X2Ys van be taken advantage of.
> [Original Message]
> From: steve weir <weirsi@xxxxxxxxxx>
> To: <leeritchey@xxxxxxxxxxxxx>; Erin.McPhalen@xxxxxxxxxxxxxxxxxxxxxxxxx
<Erin.McPhalen@xxxxxxxxxxxxxxxxxxxxxxxxx>; <si-list@xxxxxxxxxxxxx>
> Date: 6/28/2006 3:48:54 PM
> Subject: RE: [SI-LIST] Re: Decoupling Capacitor ESR/ESL
>
> Lee we agree that if one is going to traverse long Z axis distances
> the inductance is dominated by Z axis effects. Hence, we are
> concerned with the efficiency of vias. Via efficiency varies
> depending on the capacitor type and via configuration. One of the
> worst via efficiencies out there is a traditional two terminal cap
> with four vias. Poor via efficiency contributes other "benefits"
> such as aggravating the ratio of inductance to resistance of the
> mounted capacitor array aggravating peak impedance at parallel
> resonance, as well as turning the board into Swiss cheese.
>
> I will not belabor arguing conclusions we disagree on. Rather I will
> offer advice that I trust you agree with and that is to always
> evaluate comparisons using real numbers. If considered carefully,
> and used with a little creativity sometimes astonishing improvements
> can be realized over what general assumptions would otherwise have
> led us to. Judicious use of the right methods and appropriate parts
> for a given situation should always yield optimal results. If that
> happens with two terminal caps using two or four vias or some yet to
> be invented part then so be it.
>
> Regards,
>
>
> Steve.
>
> At 12:44 PM 6/28/2006, Lee Ritchey wrote:
> >Erin,
> >
> >On page 143 of my book there is a formula for the inductance that the via
> >connections add to the overall inductance of the mounting structure for a
> >capacitor. The amount shown there is 35.3 pH per mil of length. Some
> >would say it is a little more than this and others a little less.
Eithere
> >way if you have to connect the capacitors to planes that are deep in a
PCB
> >,which most of us do when we have high layer count PCBs or when it is a
4
> >layer PCB, this inductance rapidly comes to dominate. That is shown in
> >figure 34.10 where an IDC capacitor with 8 vias is only slightly better
> >than an 0603 with 4 vias.
> >
> >Our experience is that these ultra low inductance capacitors pay off only
> >when the planes they hook to are very close to the surface as is the case
> >in BGA packages. For PCBs, 0402 or 0603 capacitors represent a
reasonable
> >cost vs. performance tradeoff mounted with four vias as shown in figure
> >35.4.
> >
> >Hope this helps.
> >
> >
> > > [Original Message]
> > > From: <Erin.McPhalen@xxxxxxxxxxxxxxxxxxxxxxxxx>
> > > To: <weirsi@xxxxxxxxxx>; <si-list@xxxxxxxxxxxxx>
> > > Date: 6/28/2006 11:34:09 AM
> > > Subject: [SI-LIST] Re: Decoupling Capacitor ESR/ESL
> > >
> > > Hi Steve
> > > Thank you for your response, that website has excellent material on
> > > decoupling capacitors.
> > >
> > > I guess the issue I have using HJs model is that Lee Ritchy give an
> > > inductance of 1.19 nH for a 0603 with End-to-End vias, and 0.780 nH
for
> > > the Side-to-Side vias. When I run the numbers for a 12 mil drill
hole,
> >5
> > > mil distance from pad to ground plane, I get a via contribution of
108 pH
> > > for 0.050 mils separation and 153 pH for 0.150. Using HJ's
> > > recommendation of treating the Pads, trace stubs, and capacitor body
as
> > > transmission lines to derive the inductance, I end up with 647 pH for
a
> > > Side-to-Side vias and 737 pH for an End-to-End vias. This takes into
> > > account the changes in pad and trace lengths but keeping the capacitor
> > > "height" fixed. My only conclusion is that the via contribution is
two
> > > low when calculating the inductance for the region encased by the vias
> >and
> > > mounting structure.
> > >
> > > I was hoping to come up with an reasonable formula for calculating the
> > > mounted inductance that was consistent with Lee Ritchey. Keeping cap
> > > height constant should be able to give me something close to Lee
> >Ritchey's
> > > mounted inductances from his book.
> > >
> > > The end goal was to provide a tool for choosing decoupling capacitors
on
> > > new products here and to hopefully convert the Kemet ESLs to mounted
ESLs
> > > to provide a good source of various measured ESLs for capacitors.
> > >
> > > Erin McPhalen
> > >
> > >
> > >
> > >
> > >
> > > steve weir <weirsi@xxxxxxxxxx>
> > > Sent by: si-list-bounce@xxxxxxxxxxxxx
> > > 06/27/2006 10:40 AM
> > > Please respond to
> > > weirsi@xxxxxxxxxx
> > >
> > >
> > > To
> > > Erin.McPhalen@xxxxxxxxxxxxxxxxxxxxxxxxx, si-list@xxxxxxxxxxxxx
> > > cc
> > >
> > > Subject
> > > [SI-LIST] Re: Decoupling Capacitor ESR/ESL
> > >
> > >
> > >
> > >
> > >
> > >
> > > Erin, there are appnotes on the X2Y web site www.x2y.com that show
> > > measured capacitor ESL for several different types of ordinary
> > > capacitors and X2Ys of course for different mounting conditions.
> > >
> > > If you look closely, the formulas derived empirically for incremental
> > > inductance versus height in Lee's book are off a little but not way
> > > off from the derivation using the method of Biot-Savart that is
> > > behind Dr. Johnson's formula for via pair inductance within a cavity:
> > >
> > > L = H*u/pi * ln( S / R )
> > >
> > > Dr. Johnson derived a different formula for inductance outside a
cavity.
> > >
> > > Otherwise known as 10.2pH / mil * ln( S/R )
> > >
> > > For 0402s using sidemount vias on 1mm centers and 10 mil drills this
> > > becomes 21pH / mil. Lee's book has a value of 35.5pH/mil/via without
> > > specifying the via diameter or spacing which would work out to 17.8pH
> > > / mil. So, you can see that they are in spitting distance of each
> > > other for that specific case.
> > >
> > > In very carefully constructed test fixtures, we find that Biot-Savart
> > > still works. The trouble that you may be having is the method that
> > > you use to measure inductance. Please see any of Istvan's or my
> > > papers on that somewhat tricky subject. It is very easy to get
> > > thrown off especially when trying to measure small inductances.
> > >
> > > Steve.
> > > At 09:02 AM 6/27/2006, Erin.McPhalen@xxxxxxxxxxxxxxxxxxxxxxxxx wrote:
> > > >Hi
> > > >I have put together a board impedance calculator in Excel that
graphs the
> > > >impedance of a PCB based on various decoupling capacitor values(ESR,
ESL,
> > > >C) and embedded capacitance of the board. I am having difficulty,
> > > >determining the ESL in particular for MLC capacitor. I was using the
> > > >"Right the First Time" book to bring in the mounting ESL and Via
effects,
> > > >but find the results inconsistent in the book, especially in terms of
> > > >various measured values compared to calculated. Howard Johnson had
> > > >several empirical formulas but I found poor correlation between the
> > > >formulas given by Howard Johnson compared to those presented by Lee
> > > >Ritchey, both calculated and measured.
> > > >
> > > >Is their a reasonable method of calculating ESL that is consistent
with
> > > >measured values for determining the mounted inductance of a capacitor
> > > >including the inductance associated with the Vias to the power/ground
> > > >pairs? I have looked at the AVX and Kemet Spice models as well.
AVXs
> > > ESR
> > > >values agree well with Lee Ritchey's measured but the ESL was fixed
based
> > > >on package. The Kemet spice models provided ESL/ESR but both were
> > > >excessively high compared to the calculated/measured values from Lee
> > > >Ritchey. I know that voltage rating, vias separation, dialectic,
> > > >package, etc all effect the ESL.
> > > >
> > > >If anyone has a sound empirical formula or knows of a manufacturer
who
> > > >publishes ESL values of standard ceramic capacitors that seem
reasonably
> > > >close to measured values that would be a big help. Even relative
> > > >magnitude would work across various values of capacitors, since the
> > > intent
> > > >of the spreadsheet is to help engineers here plan their decoupling
> > > >strategy based on a target board impedance.
> > > >
> > > >Thank you in advance,
> > > >
> > > >Erin McPhalen
> > > >
> > > >Hardware Designer
> > > >R&D Hardware
> > > >SCHNEIDER ELECTRIC
> > > >
> > > >
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