[SI-LIST] Decoupling Capacitor ESR/ESL
- From: Erin.McPhalen@xxxxxxxxxxxxxxxxxxxxxxxxx
- To: si-list@xxxxxxxxxxxxx
- Date: Tue, 27 Jun 2006 09:02:37 -0700
Hi
I have put together a board impedance calculator in Excel that graphs the
impedance of a PCB based on various decoupling capacitor values(ESR, ESL,
C) and embedded capacitance of the board. I am having difficulty,
determining the ESL in particular for MLC capacitor. I was using the
"Right the First Time" book to bring in the mounting ESL and Via effects,
but find the results inconsistent in the book, especially in terms of
various measured values compared to calculated. Howard Johnson had
several empirical formulas but I found poor correlation between the
formulas given by Howard Johnson compared to those presented by Lee
Ritchey, both calculated and measured.
Is their a reasonable method of calculating ESL that is consistent with
measured values for determining the mounted inductance of a capacitor
including the inductance associated with the Vias to the power/ground
pairs? I have looked at the AVX and Kemet Spice models as well. AVXs ESR
values agree well with Lee Ritchey's measured but the ESL was fixed based
on package. The Kemet spice models provided ESL/ESR but both were
excessively high compared to the calculated/measured values from Lee
Ritchey. I know that voltage rating, vias separation, dialectic,
package, etc all effect the ESL.
If anyone has a sound empirical formula or knows of a manufacturer who
publishes ESL values of standard ceramic capacitors that seem reasonably
close to measured values that would be a big help. Even relative
magnitude would work across various values of capacitors, since the intent
of the spreadsheet is to help engineers here plan their decoupling
strategy based on a target board impedance.
Thank you in advance,
Erin McPhalen
Hardware Designer
R&D Hardware
SCHNEIDER ELECTRIC
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