[SI-LIST] Re: Decoupling Capacitor ESR/ESL

I believe the drill diameter for John's vias was 12 mils, which would
result in a higher inductance as Steve observes.  As we go to 10 mils, 
things jsut get worse.


> [Original Message]
> From: steve weir <weirsi@xxxxxxxxxx>
> To: <Erin.McPhalen@xxxxxxxxxxxxxxxxxxxxxxxxx>; <si-list@xxxxxxxxxxxxx>
> Date: 6/28/2006 3:13:28 PM
> Subject: [SI-LIST] Re: Decoupling Capacitor ESR/ESL
>
> Erin, The science behind Dr Johnson's analysis is solid.  It does 
> predict incremental effects of moving vias around pretty well.  For 
> example if you take end mounted vias and push them further apart, his 
> methods predict the incremental inductance pretty closely.  Dr 
> Johnson verifies that with his 100X models.  The issue with the 
> models is that capacitors are represented by solid metal blocks 
> virtually at the PCB surface.  That isn't what happens with real 
> capacitors.  Had he built his 100X models with additional features to 
> account for the location of the capacitor plates relative to the PCB 
> mounting surface there is little doubt that the results would have 
> been substantially higher and much closer to what you see in Lee's 
> book and real life.
> The incremental inductance for via Z axis in Lee's book are not way 
> off for specific cases.  In Lee's book I recall that John Zasio was 
> measuring primarily 0603 capacitors.  John did not specify either 
> drill size or spacing.  However, I suspect that the spacing was 
> 50mils to support routing grid.  Similarly, most likely he was using 
> 14 or 15mil drills to keep the aspect ratio under control for thick 
> boards.  For 14mil drills I get 20pH / mil and for 15mil drills 
> 19.3pH / miil.  In that case his measurements are off by 11% or less 
> for the case of a two via capacitor mount.  That's still a lot better 
> than much of the information that is out there.  You just need to 
> understand where those numbers come from and how to get the right 
> numbers for your situation.
>
> For big capacitors like tantalums, the capacitor body contributes a 
> lot of inductance.  An ordinary tantalum construction has a wire half 
> way up the body extending into the tantalum slug.  That big Z axis 
> rise and little wire makes a big induction loop.  John Pymak did a 
> nice presentation on this at the TF at DesignCon East 2005.  You can 
> find it on Istvan's web-site. Because of the large contribution from 
> the capacitor dimensions, and the large value of inductance to begin 
> with the percentage error of measurements in Lee's book for big caps 
> is quite low.
>
> Where I find the book goes a bit wrong is that John offered a blanket 
> metric of 35.5pH / mil / via that does not specify via diameter, 
> spacing, or array density.  Four vias on an 0402 do not come close to 
> halving the via inductance due to mutual coupling from + to +, and - 
> to -.  Similarly, vias spaced 100mils apart have a lot higher 
> inductance / mil than the same diameter vias spaced 40 mils apart.
>
> If you have built a spreadsheet that uses one dimensional models you 
> are still going to face other surprises, especially if you try to 
> make very low impedance PDNs.  Those kinds of spreadsheets can be 
> very handy as a starting point.  But at a minimum you will want to 
> account for 2D effects of the planes.  Ultimately we are concerned 
> with the power at the die and that means that you also need to 
> account for what is between the planes and the die, sic what the IC 
> package and die parasitics look like.  These considerations make a 
> market for products from companies like Sigrity, Ansoft, and KAW.
>
> Regards,
>
>
> Steve.
>
>
> At 11:00 AM 6/28/2006, Erin.McPhalen@xxxxxxxxxxxxxxxxxxxxxxxxx wrote:
>
> >Hi Steve
> >
> >Thank you for your response, that website has excellent material on 
> >decoupling capacitors.
> >
> >  I guess the issue I have using HJs model is that Lee Ritchy give 
> > an inductance of 1.19 nH for a 0603 with End-to-End vias, and 0.780 
> > nH for the Side-to-Side vias.   When I run the numbers for a 12 mil 
> > drill hole,  5 mil distance from pad to ground plane, I get a via 
> > contribution of 108 pH for 0.050 mils separation and 153 pH for 
> > 0.150.   Using HJ's recommendation of treating the Pads, trace 
> > stubs, and capacitor body as transmission lines to derive the 
> > inductance, I end up with 647 pH for a Side-to-Side vias and 737 pH 
> > for an End-to-End vias.  This takes into account the changes in pad 
> > and trace lengths but keeping the capacitor "height" fixed.  My 
> > only conclusion is that the via contribution is two low when 
> > calculating the inductance for the region encased by the vias and 
> > mounting structure.
> >
> >I was hoping to come up with an reasonable formula for calculating 
> >the mounted inductance that was consistent with Lee Ritchey. Keeping 
> >cap height constant should be able to give me something close to Lee 
> >Ritchey's mounted inductances from his book.
> >
> >The end goal was to provide a tool for choosing decoupling 
> >capacitors on new products here and to hopefully convert the Kemet 
> >ESLs to mounted ESLs to provide a good source of various measured 
> >ESLs for capacitors.
> >
> >Erin McPhalen
> >
> >
> >
> >
> >steve weir <weirsi@xxxxxxxxxx>
> >Sent by: si-list-bounce@xxxxxxxxxxxxx
> >
> >06/27/2006 10:40 AM
> >Please respond to
> >weirsi@xxxxxxxxxx
> >
> >To
> >Erin.McPhalen@xxxxxxxxxxxxxxxxxxxxxxxxx, si-list@xxxxxxxxxxxxx
> >cc
> >Subject
> >[SI-LIST] Re: Decoupling Capacitor ESR/ESL
> >
> >
> >
> >
> >Erin, there are appnotes on the X2Y web site www.x2y.com that show
> >measured capacitor ESL for several different types of ordinary
> >capacitors and X2Ys of course for different mounting conditions.
> >
> >If you look closely, the formulas derived empirically for incremental
> >inductance versus height in Lee's book are off a little but not way
> >off from the derivation using the method of Biot-Savart that is
> >behind Dr. Johnson's formula for via pair inductance within a cavity:
> >
> >L = H*u/pi * ln( S / R )
> >
> >Dr. Johnson derived a different formula for inductance outside a cavity.
> >
> >Otherwise known as 10.2pH / mil * ln( S/R )
> >
> >For 0402s using sidemount vias on 1mm centers and 10 mil drills this
> >becomes 21pH / mil.  Lee's book has a value of 35.5pH/mil/via without
> >specifying the via diameter or spacing which would work out to 17.8pH
> >/ mil.  So, you can see that they are in spitting distance of each
> >other for that specific case.
> >
> >In very carefully constructed test fixtures, we find that Biot-Savart
> >still works.  The trouble that you may be having is the method that
> >you use to measure inductance.  Please see any of Istvan's or my
> >papers on that somewhat tricky subject.  It is very easy to get
> >thrown off especially when trying to measure small inductances.
> >
> >Steve.
> >At 09:02 AM 6/27/2006, Erin.McPhalen@xxxxxxxxxxxxxxxxxxxxxxxxx wrote:
> > >Hi
> > >I have put together a board impedance calculator in Excel that graphs
the
> > >impedance of a PCB based on various decoupling capacitor values(ESR,
ESL,
> > >C) and embedded capacitance of the board.  I am having difficulty,
> > >determining the ESL in particular for MLC capacitor.  I was using the
> > >"Right the First Time" book to bring in the mounting ESL and Via
effects,
> > >but find the results inconsistent in the book, especially in terms of
> > >various measured values compared to calculated.   Howard Johnson had
> > >several empirical formulas but I found poor correlation between the
> > >formulas given by Howard Johnson compared to those presented by Lee
> > >Ritchey, both calculated and measured.
> > >
> > >Is their a reasonable method of calculating ESL that is consistent with
> > >measured values for determining the mounted inductance of a capacitor
> > >including the inductance associated with the Vias to the power/ground
> > >pairs?  I have looked at the AVX and Kemet Spice models as well.  AVXs
ESR
> > >values agree well with Lee Ritchey's measured but the ESL was fixed
based
> > >on package.  The Kemet spice models provided ESL/ESR but both were
> > >excessively high compared to the calculated/measured values from Lee
> > >Ritchey.   I know that voltage rating, vias separation, dialectic,
> > >package, etc all effect the ESL.
> > >
> > >If anyone has a sound empirical formula or knows of a manufacturer who
> > >publishes ESL values of standard ceramic capacitors that seem
reasonably
> > >close to measured values that would be a big help.   Even relative
> > >magnitude would work across various values of capacitors, since the
intent
> > >of the spreadsheet is to help engineers here plan their decoupling
> > >strategy based on a target board impedance.
> > >
> > >Thank you in advance,
> > >
> > >Erin McPhalen
> > >
> > >Hardware Designer
> > >R&D Hardware
> > >SCHNEIDER ELECTRIC
> > >
> > >
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