[SI-LIST] Re: DDR traces across different power plane
- From: steve weir <weirsi@xxxxxxxxxx>
- To: pangning2000@xxxxxxxxx, "Shikha soni" <iamfenta@xxxxxxxxx>
- Date: Tue, 19 Apr 2005 08:26:53 -0700
Peter, you are confusing the DC return path with the AC return path. At
500Mts DDR crossing splits even with just the address and control lines is
an invitation to signaling trouble, not to mention an EMC nightmare.
You can download my paper "Does Position Matter" from the Teraspeed web
site, www.teraspeed.com to get a better idea of the difference. There are
additional papers by Scott McMorrow on the Teraspeed site that illustrate
in detail how crossing a split creates a discontinuity and excites the
slot. You can also find information on Dr. Johnson's site www.sigcon.com,
Rod Strange's www.fastedges.org, or Eric Bogatin's "www.bethesignal.com".
If you run a transient simulation in Speed 2000, and have entered your
geometry with the split you should definitely see the signal impairment and
line to line cross talk that result from crossing the plane split. If you
are not seeing those effects, then you should contact Sigrity for help with
your simulations.
There are several approaches to trying to deliver low layer count, high
performance boards. Understanding, and defining a return path that works by
design is key to all.
Good luck.
Steve
At 10:41 PM 4/19/2005 +0800, Pang Ning wrote:
>Steve/Shikha,
>Thanks for your reply. It may cause problems as you mentioned. But I'm
>still confused. Even if the high speed traces (on layer 1) cross different
>VCC planes on layer 2, the ground return current of these traces will
>still flow on the GND plane which is intact on layer 3. The problem that
>I'm worried is the impedance discontinuous for these traces. Could you
>help to explain why you think this kind of routing will cause SI issue
>except impedance broken? Thanks a lot. I tried to run some simulation with
>SPEED2000 and didn't found serious problems.
>
>I thought of another routing scheme, parts of address & control traces of
>DDR are routed on VCC plane. In this way, most of traces won't cross power
>plane. However, there are some address trace segments which will be
>located above the routing area on VCC plane. I don't know whether this
>kind of routing will be better than previous one.
>
>The bottom layer is full of DDR traces as well so it's useless to exchange
>VCC and GND layers. It's a challenge that MCLK frequency need to achieve
>250MHz (DQS 500MHz).
>
>Thanks for your help!
>Best Regards,
>Peter Pang
>
>----- Original Message -----
> From: steve weir
> To: pangning2000@xxxxxxxxx ; si-list@xxxxxxxxxxxxx
> Sent: Tuesday, April 19, 2005 8:34 PM
> Subject: [SI-LIST] Re: DDR traces across different power plane
>
>
> Peter, if you mean a 250MHz clock and 500Mt/s data rate, then you likely
> have some serious problems. If you mean a 125MHz clock and 250Mt/s, then
> with some care, you should be able to manage getting the address and
> control lines across a split.
>
> Steve
> At 06:37 PM 4/19/2005 +0800, Pang Ning wrote:
> >Dear experts,
> >I am currently working on a 4-layer PCB layout. Due to the complicated
> >power scheme, some of the DDR traces have to be routed across different
> >power planes. In details, DDR traces are mainly on the layer 1, and
> VCC is
> >layer 2. Many address & control traces must be routed above the gap
> >between different VCC planes. I understood the impedance will be
> >discontinuous for these traces, but it's unavoidable in order to reduce
> >cost. I want to know whether there is any other problems for this kind of
> >routing? The GND plane is intact on layer 3. The return path of these
> >traces should be good since GND plane is good, right?
> >
> >The reflection may not be serious because these signal has relatively
> slow
> >switching rate. Did anybody try this kind of routing experience for DDR
> >before? Our target frequency will be 250MHz. Thanks for your comments.
> >
> >Best Regards,
> >Peter Pang
> >04/19/2005
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