[SI-LIST] Re: DDR traces across different power plane

Peter,

From the discussion, I believe that you have the following configuration

SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSS  Layer 1 (Signal)
P1PP1P1P1P1P1P1 P2P2P2P2P2P2P2P2P2P2  Layer 2 (Split Power)
GGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGG  Layer 3 (GND)
SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSS  Layer 4 (Signal)

For the signals on layer 1, the issue is that the return current will be on
the power planes not the ground. The Power to Ground natural capacitance
will allow the return current to cross the split, but the effectiveness will
depend on the dielectric thickness (Thinner is better). Other options to
manage the return issue are:
1) You can put coupling capacitors between the 2 power regions (But this
will couple supply noise between the supplies. This ill also have multiple
signals sharing the return path, increasing crosstalk)
2) You can place decoupling capacitors on either side of the split, thus
providing the return path, but again you may have multiple signals sharing
the same capacitor, increasing signal crosstalk

The split will also be a region of emissions due to the discontinuity

There are no elegant solutions with 4 layers.

 Doug

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Pang Ning
Sent: Tuesday, April 19, 2005 10:47 AM
To: Pang Ning; weirsi@xxxxxxxxxx; Shikha soni
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: DDR traces across different power plane


Steve/Shikha,
Sorry, DQS is still 250MHz, but data rate is 500Mt/s.

Best Regards,
Peter Pang
  ----- Original Message -----
  From: Pang Ning
  To: weirsi@xxxxxxxxxx ; Shikha soni
  Cc: si-list@xxxxxxxxxxxxx
  Sent: Tuesday, April 19, 2005 10:41 PM
  Subject: Re: [SI-LIST] Re: DDR traces across different power plane


  Steve/Shikha,

  Thanks for your reply. It may cause problems as you mentioned. But I'm
still confused. Even if the high speed traces (on layer 1) cross different
VCC planes on layer 2, the ground return current of these traces will still
flow on the GND plane which is intact on layer 3. The problem that I'm
worried is the impedance discontinuous for these traces. Could you help to
explain why you think this kind of routing will cause SI issue except
impedance broken? Thanks a lot. I tried to run some simulation with
SPEED2000 and didn't found serious problems.

  I thought of another routing scheme, parts of address & control traces of
DDR are routed on VCC plane. In this way, most of traces won't cross power
plane. However, there are some address trace segments which will be located
above the routing area on VCC plane. I don't know whether this kind of
routing will be better than previous one.

  The bottom layer is full of DDR traces as well so it's useless to exchange
VCC and GND layers. It's a challenge that MCLK frequency need to achieve
250MHz (DQS 500MHz).

  Thanks for your help!
  Best Regards,
  Peter Pang

  ----- Original Message -----
    From: steve weir
    To: pangning2000@xxxxxxxxx ; si-list@xxxxxxxxxxxxx
    Sent: Tuesday, April 19, 2005 8:34 PM
    Subject: [SI-LIST] Re: DDR traces across different power plane


    Peter, if you mean a 250MHz clock and 500Mt/s data rate, then you likely
    have some serious problems.  If you mean a 125MHz clock and 250Mt/s,
then
    with some care, you should be able to manage getting the address and
    control lines across a split.

    Steve
    At 06:37 PM 4/19/2005 +0800, Pang Ning wrote:
    >Dear experts,
    >I am currently working on a 4-layer PCB layout. Due to the complicated
    >power scheme, some of the DDR traces have to be routed across different
    >power planes. In details, DDR traces are mainly on the layer 1, and VCC
is
    >layer 2. Many address & control traces must be routed above the gap
    >between different VCC planes. I understood the impedance will be
    >discontinuous for these traces, but it's unavoidable in order to reduce
    >cost. I want to know whether there is any other problems for this kind
of
    >routing? The GND plane is intact on layer 3. The return path of these
    >traces should be good since GND plane is good, right?
    >
    >The reflection may not be serious because these signal has relatively
slow
    >switching rate. Did anybody try this kind of routing experience for DDR
    >before? Our target frequency will be 250MHz. Thanks for your comments.
    >
    >Best Regards,
    >Peter Pang
    >04/19/2005
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