[SI-LIST] Re: DDR traces across different power plane
- From: steve weir <weirsi@xxxxxxxxxx>
- To: pangning2000@xxxxxxxxx, <si-list@xxxxxxxxxxxxx>
- Date: Tue, 19 Apr 2005 05:34:21 -0700
Peter, if you mean a 250MHz clock and 500Mt/s data rate, then you likely
have some serious problems. If you mean a 125MHz clock and 250Mt/s, then
with some care, you should be able to manage getting the address and
control lines across a split.
Steve
At 06:37 PM 4/19/2005 +0800, Pang Ning wrote:
>Dear experts,
>I am currently working on a 4-layer PCB layout. Due to the complicated
>power scheme, some of the DDR traces have to be routed across different
>power planes. In details, DDR traces are mainly on the layer 1, and VCC is
>layer 2. Many address & control traces must be routed above the gap
>between different VCC planes. I understood the impedance will be
>discontinuous for these traces, but it's unavoidable in order to reduce
>cost. I want to know whether there is any other problems for this kind of
>routing? The GND plane is intact on layer 3. The return path of these
>traces should be good since GND plane is good, right?
>
>The reflection may not be serious because these signal has relatively slow
>switching rate. Did anybody try this kind of routing experience for DDR
>before? Our target frequency will be 250MHz. Thanks for your comments.
>
>Best Regards,
>Peter Pang
>04/19/2005
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