[SI-LIST] Re: DDR point to point termination
- From: Mike Brown <bmgman@xxxxxxxxxx>
- To: janton@xxxxxxxxxxxxxxxxxx
- Date: Wed, 14 Jul 2004 19:53:20 -0500
You state that the inputs to a controller should be gated, and I concur. Only
problem is that there's not much to gate the controller with. Nothing from the
bus, at least.
The controller needs to know when to enable the DQS receiver(and implicitly,
the DQ receivers), and that's not always an easy thing to figure out.
Therein lies the art of designing a "well designed controller".
Mike
Jim Antonellis wrote:
> 2 more cents to the collection....
>
> Again DDR2, point-to-point data, 250MHz, ~7"
>
> We found that across PVT and fab tolerances that parallel
> terms provided the most margin (and we could "afford" them
> in cost and power).
>
> Secondly, in regards to "floating", the DDR2 memories gate
> the inputs with RAS, CAS and CS as does a well designed cntlr.
> So, with series terms (which truely float) or parallel terms
> (which "park" the inputs at Vddq/2) your inputs are gated.
>
> Jim
>
> -
> Jim Antonellis jim.antonellis@xxxxxxxxxxxxx
> Sandburst Corp www.sandburst.com
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> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx
> [mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Peterson, James F
> (FL51)
> Sent: Tuesday, July 13, 2004 1:20 PM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: DDR point to point termination
>
>
> maybe it's 4 devices because of data width not depth...
>
> I am also interested in DDR SSTL term schemes. I am simulating a point =
> to
> point architecture with no pull-ups in the interface. I am assuming a =
> longer
> run than 2 inches. More like 6 inches. the data bus is bi-directional so =
> i
> have a series terminating resistor at both drivers. This seems to be =
> very
> effective. The recommended pull-up adds no benefit, and adds to the =
> power so
> I don't plan on using it. The catch, though, is to make sure the bus =
> doesn't
> tri-state, cause it'll float w/o the pull-up.
>
> jim peterson
> honeywell
>
> -----Original Message-----
> From: Landrum, Chris [mailto:chris_landrum@xxxxxxxxxx]
> Sent: Tuesday, July 13, 2004 1:02 PM
> To: arich1970@xxxxxxxxxxx; si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: DDR point to point termination
>
>
>
> I have implemented a point to point DDR interface (200MHz) using series
> resistors located in the middle of the data traces. I have seen the
> same app note you speak of requiring the trace lengths to be less than
> 2in, which seems to work well in my application. =3D20
>
> However, you describe a DDR interface consisting of 4 devices. This is
> not point-to-point as the devices will share data lines. This interface
> should be simulated.
>
>
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
> On Behalf Of Aric Hadav
> Sent: Tuesday, July 13, 2004 11:24 AM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] DDR point to point termination
>
> Hi,
>
> I'm designing an embedded system with DDR. I'm using a CPU connected to
> an=3D20
> on board four 16 bit DDR devices (no DIMM).
> I have 2 questions though -
> 1. can I use only a series termination on the data bus (I saw a few AN
> that=3D20
> state that if the disctance between the controller and the DDR IC's is
> upto=3D20
> 2" its ok). has anyone did it with a 200MHz clock ?
> 2. since the address and control lines operate in half the data rate and
> the=3D20
> DDR controller is very lightly loaded (only 4 chips) can I use only
> series=3D20
> termination for address and control ? has anyone did it with good
> resaults ?
>
> thanks,
>
> Aric
>
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