[SI-LIST] Re: Crosstalk between two planes
- From: "Lambert Simonovich" <bertsimonovich@xxxxxxxxxx>
- To: "'Jaison Fernandez \(RBEI/EED2\)'" <Jaison.Fernandez@xxxxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Thu, 17 Jun 2010 12:25:30 -0400
Jaison,
At first glance, your stack-up will have manufacturing issues because it is
not symmetrical about the center of the board. Having an unequal
distribution of planes on layers 1-4 compared to layers 5-8 means the board
will be subject to warpage during manufacturing.
A better stackup to satisfy both manufacturing and crosstalk issues would be
as follows;
1. Top
2. Gnd1
3. Sig1
4. PWR
5. Gnd2
6. Sig2
7. Gnd3
8. Bottom
If you do not have a 2D field solver, I suggest you work with your preferred
board fabricator to refine the stackup to achieve your target impedances
based on your routed line widths.
Regards,
Bert Simonovich, Consultant & Founder
LAMSIM Enterprises Inc.
http://lamsimenterprises.com/
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Jaison Fernandez (RBEI/EED2)
Sent: June-17-10 4:06 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Crosstalk between two planes
Dear Experts,
I have a layer stack up like as follows:
1. Top
2. Gnd1
3. Power
4. Gnd2
5. Sig1
6. Sig2
7. Gnd3
8. Bottom
My board is one which contains ATMEL AT91SAM9M10, 128MB SDRAM (166MHz), GPS
Chip solution, High current motor Drivers etc.
I placed Atmel and SDRAM in bottom layer and routed the SDRAM signals in
Sig1 and Sig2 planes.
Could any one tell me the chances crosstalk between sig1 and Sig2 planes and
possible ways to avoid it.
Due to some tool limitations I can't able to due any POST SI analysis.(Stack
up of Layer1 to Layer 3 is fixed due to some high current applications)
Regards,
Jaison Fernandez
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