[SI-LIST] Re: Crosstalk between two planes

Jaison,
if you want to avoid crosstalk on adjacent signal layers (without a plane 
separating them), the usual approach is to keep the routing at right 
angles, i.e. one layer carries all the vertical trace segments, the other 
all the horizontal ones. There has been an extensive thread on this 
mailing list about this topic just a couple weeks ago, so if you want to 
read more just go to the mailing list archive.

In a nutshell, if traces are running close to each other (less than ~3-4 
line widths) in parallel you risk will get significant crosstalk. Any 
simple 2D field solver an tell you how much for a given geometry. If the 
traces are at right angles to each other then crosstalk is negligible.

But one much more important thing is wrong with your stackup, it is highly 
asymmetrical as others have already pointed out. Having all but one planes 
(i.e. mostly copper filled) on the top of the stackup and the signal 
layers (sparse copper coverage) on the bottom will cause manufacturing 
problems (board warpage during processing). Chances are your manufacturer 
will tell you to change the stackup. You really need to keep it as 
symmetric as possible.

Regards,

Wolfgang






"Jaison Fernandez (RBEI/EED2)" <Jaison.Fernandez@xxxxxxxxxxxx> 
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06/17/2010 01:06 AM

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[SI-LIST] Crosstalk between two planes






Dear Experts,
I have a layer stack up like  as follows:

1. Top
2. Gnd1
3. Power
4. Gnd2
5. Sig1
6. Sig2
7. Gnd3
8. Bottom


My board is one which contains ATMEL AT91SAM9M10, 128MB SDRAM (166MHz), 
GPS Chip solution, High current motor Drivers etc.

I placed Atmel and SDRAM in bottom layer and routed the SDRAM signals in 
Sig1 and Sig2 planes.
Could any one tell me the chances crosstalk between sig1 and Sig2 planes 
and possible ways to avoid it.
Due to some tool limitations I can't able to due any POST SI 
analysis.(Stack up of Layer1 to Layer 3 is fixed due to some high current 
applications)

Regards,
Jaison Fernandez
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