Dear Experts, I have a layer stack up like as follows: 1. Top 2. Gnd1 3. Power 4. Gnd2 5. Sig1 6. Sig2 7. Gnd3 8. Bottom My board is one which contains ATMEL AT91SAM9M10, 128MB SDRAM (166MHz), GPS Chip solution, High current motor Drivers etc. I placed Atmel and SDRAM in bottom layer and routed the SDRAM signals in Sig1 and Sig2 planes. Could any one tell me the chances crosstalk between sig1 and Sig2 planes and possible ways to avoid it. Due to some tool limitations I can't able to due any POST SI analysis.(Stack up of Layer1 to Layer 3 is fixed due to some high current applications) Regards, Jaison Fernandez ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List technical documents are available at: http://www.si-list.net List archives are viewable at: //www.freelists.org/archives/si-list Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu