[SI-LIST] Re: Crosstalk between two planes
- From: Shahbaz Assad <shahbaz_assad@xxxxxxxxxxx>
- To: <aneesh.govindan@xxxxxxxxx>, <jaison.fernandez@xxxxxxxxxxxx>
- Date: Thu, 17 Jun 2010 13:41:21 +0000
Hi Bela/jeson,
I am not a signal integrity expert But what I think is speed is not the
only concern but there are many other actors that depends like if you
route tehe high speed on top layer, they will e more suseptible to the
EMI. And if we wil not apply the solder mask, then they will ne all
naked and can be easily dusturbed my the emvoirnmental factors, You can
route those on outer layer but that are not strongly recommended.
because ther will be also some silkscreen that effect the impedence.
But of we do the SI analysis by taking under consideration all the
external factors then I think there will be no problem in routing on
external layer.
I agree with Jaisons stackup if but dont know what are the reference planes but
that stackup is looking much better. The layer that is sandwich between the
grounds are most suitable for high speed signals
Thanks,
Shahbaz Assad
System design Engineer - WhizzSystems, Inc.
> Date: Thu, 17 Jun 2010 19:07:45 +0530
> Subject: [SI-LIST] Re: Crosstalk between two planes
> From: aneesh.govindan@xxxxxxxxx
> To: Jaison.Fernandez@xxxxxxxxxxxx
> CC: si-list@xxxxxxxxxxxxx
>
> Hi Jaison,
> Hope this stackup will work for you.
>
>
> 1. Top
> 2. Gnd1
> 3. Power
> 4. Sig1
> 5. Gnd2
> 6. Sig2
> 7. Gnd3
> 8. Bottom
>
> By following the above stackup crosstalk can be avoided between Sig1 and
> Sig2.
>
> --
> Warm Regards
> Aneesh G
>
>
> On Thu, Jun 17, 2010 at 1:36 PM, Jaison Fernandez (RBEI/EED2) <
> Jaison.Fernandez@xxxxxxxxxxxx> wrote:
>
> > Dear Experts,
> > I have a layer stack up like as follows:
> >
> > 1. Top
> > 2. Gnd1
> > 3. Power
> > 4. Gnd2
> > 5. Sig1
> > 6. Sig2
> > 7. Gnd3
> > 8. Bottom
> >
> >
> > My board is one which contains ATMEL AT91SAM9M10, 128MB SDRAM (166MHz), GPS
> > Chip solution, High current motor Drivers etc.
> >
> > I placed Atmel and SDRAM in bottom layer and routed the SDRAM signals in
> > Sig1 and Sig2 planes.
> > Could any one tell me the chances crosstalk between sig1 and Sig2 planes
> > and possible ways to avoid it.
> > Due to some tool limitations I can't able to due any POST SI
> > analysis.(Stack up of Layer1 to Layer 3 is fixed due to some high current
> > applications)
> >
> > Regards,
> > Jaison Fernandez
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