[SI-LIST] Re: CLK Input not 3.3V tolerant
- From: "Ingraham, Andrew" <Andrew.Ingraham@xxxxxxxxxx>
- To: "SI-LIST (E-mail)" <si-list@xxxxxxxxxxxxx>
- Date: Tue, 29 Jan 2002 14:36:58 -0500
What you suggested (using a resistive voltage divider) does indeed work.
But in certain cases may not be the best solution.
Power sequencing might be an issue. If 3.3V comes up first, it might be
bad for the 2.5V device to have a clock signal but no power.
The resistors in conjunction with the input capacitance introduce some
delay and edge rate degradation.
Also, you have to figure out where is best to put the resistors (source
or load end), and what values to use. Unless the resistor values are
very small, the source impedance to the 2.5V device could be much
greater than that of a clock driver. Might or might not matter. But
there are some interesting things you can do with this, in terms of
partially terminating the signal trace at one or both ends.
Andy
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