[SI-LIST] CLK Input not 3.3V tolerant
- From: Yannick Gagnon <ygagnon@xxxxxxxxxxxxx>
- To: "SI-LIST (E-mail)" <si-list@xxxxxxxxxxxxx>
- Date: Tue, 29 Jan 2002 11:33:42 -0500
Hello All,
I have a clock signal that is generated by a clock buffer (pwr supply =
3.3V) and is sent to a
device that is not 3.3V tolerant (pwr supply = 2.5V). The series termination
is there to reduce
the ringing and I have put a resistor R tide to the ground just before the
input pin in order to
reduce the signal to 2.5V.
|>---/\/\/-----------------------------|>
|
[R]
|
|
GND
I did simulation in HSpice and it does what I want, the signal is reduced to
2.5V and the signal
is clean, but from more experienced designers this practice is unusual.
I was wondering if anybody had ever done this or something similiar.
I would appreciate your feedbacks.
Best regards,
Yannick
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