[SI-LIST] Re: 8 layer PCB stackups and microvias
- From: "Mangipudi, Prasad" <Prasad_Mangipudi@xxxxxxxxxxx>
- To: 'Marc Battyani' <marc.battyani@xxxxxxxxxxxxxxxxxx>, "'si-list@xxxxxxxxxxxxx'" <si-list@xxxxxxxxxxxxx>
- Date: Thu, 10 Jul 2008 15:11:38 -0700
Hi Marc,
The 8 layer stackup S/G/S/G/P/S/G/S (S =3D signal, P =3D power, G =3D groun=
d) is good and does not have any inherent weakness. The dielectric thicknes=
s between 3-4 and 5-6 can be increased to adjust for the overall thickness.=
All the signal layers are good for routing high speed signals as they refe=
rence to ground. Adjust the trace width and dielectric thickness for main=
taining constant impedance across layers. You can avoid blind/buried vias a=
nd associated high cost of PCB.
The alternate stackup G/S/S/G/P/S/S/G has the disadvantage of broken ground=
planes on top and bottom layers due to components.
Good Luck!
Prasad
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On=
Behalf Of Marc Battyani
Sent: Thursday, July 10, 2008 7:23 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] 8 layer PCB stackups and microvias
Hello,
We are designing a small 8L board with the following stackup:
S/G/S/G/P/S/G/S (S =3D signal, P =3D power, G =3D ground)
The most notable components are a few DDR2 (533) around an FPGA.
If we use microvias on the layers 1-2, 2-3, 6-7,7-8, we can route most of t=
he fast signals on the layers 1 and 3. With no microvias, we have to use al=
l the layers.
To keep the 50 Ohm tracks at a reasonable width, we use 100=B5m (4mils) die=
lectric thickness for the layers 1-2-3 and 6-7-8.
Are we missing a better PCB stackup?
Anybody tried something like G/S/S/G/P/S/S/G?
Can you recommend a good PCB shop able to make a few prototypes (+-10) at a=
reasonable cost?
(We have been given very high prices for this so far)
Thanks,
Marc
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