[SI-LIST] Re: 8 layer PCB stackups and microvias
- From: Russell Dudek <rdudek@xxxxxxxxxxxxxxx>
- To: Marc Battyani <marc.battyani@xxxxxxxxxxxxxxxxxx>, "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
- Date: Thu, 10 Jul 2008 11:16:34 -0400
Hi Marc,
I am not surprised by your luck in finding a reasonable cost for your proje=
ct. This does not sound like a commodity product to me as it has a few cha=
llenges that are associated with the microvia processing side. Furthermore=
, the tooling required for such a built and its low volume will drive the c=
osts even higher.
However, I do have some suggestions for your layouts including multilayer m=
icrovias and stacked microvias. Lastly, if it is a prototype and has flexi=
bility in the material selection. I have available a beta version spread-f=
iber high-speed material in sample quantities that is microvia friendly tha=
t you team may find beneficial.
Cheers,
Russell
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On=
Behalf Of Marc Battyani
Sent: Thursday, July 10, 2008 10:23 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] 8 layer PCB stackups and microvias
Hello,
We are designing a small 8L board with the following stackup:
S/G/S/G/P/S/G/S (S =3D signal, P =3D power, G =3D ground)
The most notable components are a few DDR2 (533) around an FPGA.
If we use microvias on the layers 1-2, 2-3, 6-7,7-8, we can route most
of the fast signals on the layers 1 and 3. With no microvias, we have to
use all the layers.
To keep the 50 Ohm tracks at a reasonable width, we use 100=B5m (4mils)
dielectric thickness for the layers 1-2-3 and 6-7-8.
Are we missing a better PCB stackup?
Anybody tried something like G/S/S/G/P/S/S/G?
Can you recommend a good PCB shop able to make a few prototypes (+-10)
at a reasonable cost?
(We have been given very high prices for this so far)
Thanks,
Marc
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