[PCB_FORUM] Re: ref des problem while merging portions of multiple schematics (Concept)
- From: "westfeldt" <westfeldt_nbcd@xxxxxxxxx>
- To: icu-pcb-forum@xxxxxxxxxxxxx
- Date: Thu, 23 Mar 2006 08:09:34 -0700
I have done this a few times lately. My method was to reannotate and then
back annotate to schematic the individual boards, using different refdes
series (starting with 301, 501, etc). Then the sub-drawing functionality
works great. After you are all done, you can reannotate and back annotate
the whole new design, or not.
Patrick Westfeldt, Jr.
720-406-0887
-----Original Message-----
From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Mark Salberg
Sent: Thursday, March 23, 2006 6:53 AM
To: Cadence User Group
Subject: [PCB_FORUM] ref des problem while merging portions of multiple
schematics (Concept)
Hello all,
I am wondering how you all would handle this?
More and more, we are cloning schematic circuits from multiple previous
designs.
Reference designator management is a pain with Concept.
1. First, we bring in the pages or portions of pages we want to steal from
multiple previous designs.
Now we need to verify there are NO duplicate ref des.
2. So, we soft locate designators (because packager will fail with any
assigned duplicates).
3. But if we are also cloning placement of some components, then those
designators must remain hard located.
4. All Multi-section or multi-gate components must have a hard located ref
des in order to package into a single ic.
Problem:
How do you manage reference designators for this situation?
Thanks,
Mark
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