[PCB_FORUM] Re: ref des problem while merging portions of multiple schematics (Concept)
- From: "Davies, Charles (cdavies)" <cdavies@xxxxxxxxxx>
- To: <icu-pcb-forum@xxxxxxxxxxxxx>
- Date: Thu, 23 Mar 2006 09:05:55 -0500
Mark,
Instead of using the ref des to force the assignment of multi-gate
components, consider using the GROUP property. Components with like
values will be assigned to the same package, irregardless of the ref
des, as long as the ref des is soft.
Also, if you are reusing elements of other designs in new designs, you
might want to consider looking at using hierarchical schematics and
additionally, if appropriate, the design reuse capability. These are
particularly well suited to this type of problem, but will require a bit
of advanced planning.
Regards,
Charlie
321.727.6235
-----Original Message-----
From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Mark Salberg
Sent: Thursday, March 23, 2006 8:53 AM
To: Cadence User Group
Subject: [PCB_FORUM] ref des problem while merging portions of multiple
schematics (Concept)
Hello all,
I am wondering how you all would handle this?
More and more, we are cloning schematic circuits from multiple previous
designs.
Reference designator management is a pain with Concept.
1. First, we bring in the pages or portions of pages we want to steal
from multiple previous designs.
Now we need to verify there are NO duplicate ref des.
2. So, we soft locate designators (because packager will fail with any
assigned duplicates).
3. But if we are also cloning placement of some components, then those
designators must remain hard located.
4. All Multi-section or multi-gate components must have a hard located
ref des in order to package into a single ic.
Problem:
How do you manage reference designators for this situation?
Thanks,
Mark
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