[PCB_FORUM] ref des problem while merging portions of multiple schematics (Concept)

  • From: Mark Salberg <msalberg@xxxxxxxxxxxx>
  • To: Cadence User Group <icu-pcb-forum@xxxxxxxxxxxxx>
  • Date: Thu, 23 Mar 2006 08:53:21 -0500

Hello all,
I am wondering how you all would handle this?
More and more, we are cloning schematic circuits from multiple previous designs.
Reference designator management is a pain with Concept.

1. First, we bring in the pages or portions of pages we want to steal from multiple previous designs.
Now we need to verify there are NO duplicate ref des.
2. So, we soft locate designators (because packager will fail with any assigned duplicates).
3. But if we are also cloning placement of some components, then those designators must remain hard located.
4. All Multi-section or multi-gate components must have a hard located ref des in order to package into a single ic.
Problem:
How do you manage reference designators for this situation?

Thanks,
Mark


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