[PCB_FORUM] Re: NO_RAT property appearing from schematic

  • From: "William Billereau" <william.billereau@xxxxxxx>
  • To: <icu-pcb-forum@xxxxxxxxxxxxx>
  • Date: Thu, 28 Apr 2005 18:00:03 +0200

all power nets are treated like this.
Automatically, it have NO_RAT property.

I do not know where it comes from, but it seems to be done by the packager or the netrev process.

   William.

----- Original Message ----- From: "Daniel So" <danielso@xxxxxxxxxxxxx>
To: <icu-pcb-forum@xxxxxxxxxxxxx>
Sent: Thursday, April 28, 2005 5:22 PM
Subject: [PCB_FORUM] Re: NO_RAT property appearing from schematic



I started this from another design. However, when I came across this
problem I imported the netlist onto a brd created from scratch and still
got the same results.


Daniel So
1065 La Avenida
Mtn View, Ca 94043
(650) 693-2054
email: danielso@xxxxxxxxxxxxx
-----Original Message-----
From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of William Gerner
Sent: Thursday, April 28, 2005 8:19 AM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: NO_RAT property appearing from schematic

Did you start your design from scratch or use some other board as
the start point?

Daniel So wrote: 
I am reading in a netlist from Concept which is suppose to have no
constraints or properties. However, I am getting a NO_RAT property on
the GND net. Doing a search on the ascii files of the schematic pages
shows no instances of this property. The property does not appear in
any
of the dat files created from Concept. Any ideas where this property
is 
coming from?



Thanks for any ideas



Daniel So

1065 La Avenida

Mtn View, Ca 94043

(650) 693-2054

email: danielso@xxxxxxxxxxxxx




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