[PCB_FORUM] Re: NO_RAT property appearing from schematic
- From: "Andrew Noonan" <andrew@xxxxxxxxxxx>
- To: <icu-pcb-forum@xxxxxxxxxxxxx>
- Date: Thu, 28 Apr 2005 09:14:55 -0700
Hi Deac,
It definitely depends on the signaling edge rates coming down the pairs,
and to some extent, the data rate. The faster the edge rate, the further
away they should be. For example, if the data rate is below 1Gbit/Sec,
diff-pairs on inner layers, with geometry of 5/5/5 (line-space-line),
you may be able to use a 15 mils air gap between pairs. But as the data
rate (and subsequently edge rate) increases, you will need to also
increase the space. It gets worse on outer layers, with air as part of
the dielectric.
So, the short answer is, no rules of thumb, it really depends on the
technology you're routing for.
Andrew Noonan
Sr. PCB Designer
Topspin Communications
(w)650-316-3398
(c)650-814-3677
-----Original Message-----
From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Deac Descoteaux
Sent: Thursday, April 28, 2005 8:15 AM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: NO_RAT property appearing from schematic
Hi All!
Is there a rule of thumb for the distance from a diff pair to the next
diff pair? I heard that you should have twice the distance of the
overall width or the preceding diff pair.
Thanks
Deac
Work phone: (603) 886-8711 ext.202
Cell : (603) 557-7568
_____
From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Gerry Meier
Sent: Thursday, April 28, 2005 11:07 AM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: NO_RAT property appearing from schematic
Was the property added in Allegro?
Gerry Meier
Sr. PCB Designer
Freedom CAD Services, Inc.
Voice: (603) 864-1300 x1350
Alt. Voice: (386) 753-0048
Email: gerry.meier@xxxxxxxxxxxxxx
visit our website at<http://www.freedomcad.com
<http://www.freedomcad.com/>
_____
From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Daniel So
Sent: Thursday, April 28, 2005 11:04 AM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] NO_RAT property appearing from schematic
I am reading in a netlist from Concept which is suppose to have no
constraints or properties. However, I am getting a NO_RAT property on
the GND net. Doing a search on the ascii files of the schematic pages
shows no instances of this property. The property does not appear in any
of the dat files created from Concept. Any ideas where this property is
coming from?
Thanks for any ideas
Daniel So
1065 La Avenida
Mtn View, Ca 94043
(650) 693-2054
email: danielso@xxxxxxxxxxxxx
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