[PCB_FORUM] Re: Diff pair Constraints and CM
- From: "Austin Franklin" <austin@xxxxxxxxxxxx>
- To: <icu-pcb-forum@xxxxxxxxxxxxx>
- Date: Thu, 10 Mar 2005 17:05:11 -0500
Hi Andrew,
> This is not necessarily true for diff pair stuff, when you have
> different widths and spacing for different layers. For instance, outer
> layers tend to have different spacing characteristics than inner layers
> (not always.. but for the point of illustration).
I just did things this way...
> In this case, you would NOT enter the values in the Electrical
> constraints/Diff pair area, but back in Physical constraints, where
> we're all used to doing it. The important thing here is that you would
> simply leave those entries blank in the Electrical constraints/Diff pair
> setup.
Ah, this I did not do. I'll review what I did based on this, thanks! Which
takes precedence? If I enter it in the EC/DP set-up, and I have an outer
layer value set different in PC, which value will it use for the outer
layers?
Regards,
Austin
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