[PCB_FORUM] Re: Diff pair Constraints and CM

  • From: Kevin McCowan <kmccowan@xxxxxxxxxxxxxx>
  • To: icu-pcb-forum@xxxxxxxxxxxxx
  • Date: Fri, 11 Mar 2005 08:08:15 -0500

If you let allegro set the impedance and you don't get the
layer stackup set properly it will set the line width to
some funky settings like 5.32 mils. At least this has been
my experience. I never let it do that.
I call one of the board houses we normally use and tell them
my requirements and let them give me a stackup based on
their process. This has always given me the best results.
The board house is happy and no weird line widths.

Kevin

Austin Franklin wrote: 
Hi Kevin,

I think the diff pair constraints work in the CM best if you have the 600
series tool that has automatic impedance adjustment for different layers.
I'm still not sure that necessarily works well either...as fabricators like
to give you the trace/space, not have you determine them.

Regards,

Austin



-----Original Message-----
From: Kevin McCowan [mailto:kmccowan@xxxxxxxxxxxxxx]
Sent: Thursday, March 10, 2005 5:13 PM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: Diff pair Constraints and CM


Well, I guess I opened a can of worms, didn't I?
What I have done to circumvent this issue is to
get a stackup that has the same width and space for
all internal layers and not allow the pairs on the
outside of the board where it is difficult to get
them the same.
I agree with everyone (and it seems like it was everyone!)
as to how to do them with different rules on different
layers. I just found my way to allow me to use the diff
pair constraints.
Sorry for any confusion.

Kevin

Austin Franklin wrote:

Hi Andrew,



This is not necessarily true for diff pair stuff, when you have
different widths and spacing for different layers. For instance, outer
layers tend to have different spacing characteristics than inner layers
(not always.. but for the point of illustration).



I just did things this way...



In this case, you would NOT enter the values in the Electrical
constraints/Diff pair area, but back in Physical constraints, where
we're all used to doing it. The important thing here is that you would
simply leave those entries blank in the Electrical constraints/Diff pair
setup.


Ah, this I did not do. I'll review what I did based on this, 

thanks!  Which

takes precedence? If I enter it in the EC/DP set-up, and I 

have an outer

layer value set different in PC, which value will it use for the outer
layers?

Regards,

Austin



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