[PCB_FORUM] Re: Allegro Sub drawing / Via stitch problem
- From: Mark Salberg <msalberg@xxxxxxxxxxxx>
- To: icu-pcb-forum@xxxxxxxxxxxxx
- Date: Wed, 29 Jul 2009 06:22:30 -0400
No, I just routed a trace (inside the shape) from a pin to the vias to
force it...Then just export / import to 0,0.
Anyone know how to search for these "floating" vias? Danging via does
not work. Would like to locate any instances I may have missed.
Thanks,
Mark
cadman10@xxxxxxxxxxx wrote:
Hello Mark,
Normaly this happens becouse when the vias do not have a net
association they inherit the net name of the first shape they find,B
Have you tried to disable the dynamic shapes on the board first , then
import your subdrawing, then enable the dynamic shapes and force your
imported shape to update first
good luck
cadman
On Jul 27, 2009, *Mark Salberg* <msalberg@xxxxxxxxxxxx> wrote:
Not quite that easy Jean,
Actually stitching to many different power supplies on 8 different
layers.
Just want to keep the import the same as the export.
Importing clip all at once by 0,0 origin.
Jean Bratton wrote:
*/_IF< /u>_/*_ all of your stitching vias are to GND, then you
can move all of your non-GND positive planes off-board before
reading in the clip. Then the unconnected vias will get
associated with GND, and then you can move the other planes
back on the board. _
_ _
_Jean Bratton_
_Senior PCB Designer_
_Freedom CAD Services, Inc._
_Office: 603-864-1349_
_Email: jean.bratton@xxxxxxxxxxxxxxx
_Visit us at http://www.freedomcad.com_
_ _
_ _
_-----Origi nal Message-----
From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Mark
Salberg
Sent: Monday, July 27, 2009 9:04 AM
To: Cadence User Group
Subject: [PCB_FORUM] Allegro Sub drawing / Via stitch problem_
_ _
_Hello all,_
_When Exporting a Sub-Drawing I found that any vias in a shape
used for _
_stitching...connected to a shape, but has no traces to a
pin...looses _
_connectivity and sometimes connect to a different plane after
import _
_sub-drawing._
_The only way I have found to fix it is to ALSO route a t race
from a pin _
_to the via to force the connection._
_ _
_Is there a way to locate any occurrences of this prior to
exporting a _
_Sub-Drawing?_
_ _
_Thought maybe dangling wire reporting as dangling via...but a
Dangling _
_via is defined a a via with only one connection from a pin.
These vias _
_simply dropped in a shape for thermal reasons do not get
flagged._
_ _
_Any thoughts as to how to find them in a design?_
_ _
_Thanks,_
_Mark_
_ _
_ _
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