Re: [steem] small bugs
- From: "Steem Authors" <russ@xxxxxxxxxxxxxxxxxxxxxxx>
- To: "Steem Discussion" <steem@xxxxxxxxxxxxx>
- Date: Mon, 9 Dec 2002 20:02:16 -0000
Hi Stephen,
> >> in Windows XP (but not 98) you can't create a type 2
> > > hidden file on drives C upwards.
> >
> > This could be tricky, must be a permissions problem or something. If you
> log
> > in as an administrator can you do it?
>
> I think I am an adminstrator by default. It doesn't matter a lot to me,
but
> my main system "save" saves 2 files and I make one of them hidden so as
not
> to clutter up the desktop. Once diagnosed easily patched.
Well it might be something we can fix, I'll get Ant to have a look at it as
soon as I can (he has XP).
> I note 2 weeks after buying Windows XP that it is so bug-ridden that I
have
> got to download a 28Mb patch to put it all right. NOT impressed. Maybe
when
> I have spent the necessary 2 hours on the phone this will work properly.
Good luck!
> > Just a note on the tracing of exceptions, I think I have fixed it. As
far
> as
> > I could tell Steem v2.4 is correct apart from chk, trapv, division by
> zero,
> > they wouldn't be traced. Is that what you have found?
>
> ...and Traps 1-16.
>
> It seems that
>
> for traceable exceptions (trap #1 - #16, trapv, div0, chk)
> - trace is switched off after the instruction following the
> exception-generating instruction (1)
> - trace is switched back on after the instruction following RTE (1)
>
> for non-traceable instructions (bus, address, privilege, illegal, A & F
> emulators)
> - trace is switched off after the exception-generating instruction (2)
> - trace is switched back on after the instruction following RTE (same as
> above) (1)
>
> (1) incorrect in Steem 2.4
> (2) correct in Steem 2.4
That's odd, I can't find any problems with tracing traps in Steem v2.4. I
did find however that you can trace line a and f exceptions, that certainly
is wrong. This is what Steem v2.4 is doing when tracing traps:
1: Set trace bit.
2: trap #?.
<Trap exception happens> - Jump to vector, trace bit cleared, stacked sr has
trace bit set.
<Trace exception happens> - Jump to vector, stacked sr has trace bit clear.
3: Trace routine.
I've tested it on my STE and it seems to be doing the same thing. The trace
exception is generated, the stacked pc is the first instruction of the trap
routine and the trace bit is clear in the stacked sr. Of course trapv, div0
and chk should all do the same thing, they don't on v2.4.
Thanks for all your help,
Russ
--
Steem - http://www.blimey.strayduck.com/
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