[SI-LIST] Re: usb eye pattern tuning
- From: "Eric F. Steimle" <eric.steimle@xxxxxxxxxx>
- To: "<lihuizju@xxxxxxxxx>" <lihuizju@xxxxxxxxx>
- Date: Wed, 16 Jan 2013 10:42:24 +0000
Did you measure the impedance? If its a trace/cable problem a Tdr would show
you the actual impedance along the whole cable board combo. Try using some
copper tape under the fpc cable (gnd at both ends). That might point to a
return path issue.
Did you put gnd fill around your traces? That can mess with your impedance as
well.
When you say too long do you mean the rise and fall time is too slow?
Eric
On Jan 16, 2013, at 2:23 AM, "Li Hui" <lihuizju@xxxxxxxxx> wrote:
> Hi Mik,
> Thanks for your advices, I'll check our power supply first to make sure
> whether it works or not.
> Thanks again.
> B. R.
> Mik Nazaryan <mik.nazaryan@xxxxxxxxx>编写：
>
>> Hi Li,
>> I can only tell you my experience in USB2.0 compliance testing. We had
>> one product that also had problems with the USB compliance test (eye
>> diagram fail). So, I spent one week to recheck all the layout and could
>> not find anything wrong. Finally I just decided to add another 100nF cap
>> between power supply and GND. And this cap dramatically reduce the
>> errors in the eye diagram. Maybe the problem was related to the
>> chipset's power supply, but who knows, maybe it will help you as well.
>>
>> Mik.
>>> Hi Experts:
>>> we are making a device which has an USB 2.0 port. This port is
>>> consisted of two part of traces, one is on the main board(about 100mm), the
>>> other one is a FPC(about 120mm) who has an micro usb receptacle on it. We
>>> are using a pair of connectors to connected them togother. Unfortunately
>>> during the USB compliance test, we find the rising and falling edges of the
>>> signal are too long which violated the test. We checked our layout, the
>>> differential trace impedance on main board is 87 ohms, and they are
>>> protected well which means they are surrounded by gound stearoly. FPC's
>>> impedance seems good too, little larger than 90 ohms. We changed the
>>> settings in processor such as slew rate, setup and hold time, and
>>> terminated impedance. But can't find a set of paraneters which could pass
>>> the test.
>>> So can any one help to give us some advices which can improve the
>>> signal quality? We know the shorter the length of trace can help, but the
>>> ID has been decided, it can't change now.
>>> Besr
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