tences, missing words, and missing format even though they are sent in just
text format. Can we have this fixed?
I am reposting the email sent earlier today hoping it will show up complete and
with correct format:
Hi Leonard,you can derive the answer yourself. Think of what currents flow
through the metallic chassis and why, and then use the fundamental laws to make
sure that the chassis currents cannot couple into your system. For example,
if you connect the chassis to your system ground with only one wire (one
connection point) can the chassis currents flow into your system? Start from
this and you will find the answer and more than that - you will understand the
fundamental Physics mechanisms involved in your structure.Regards,Cosmin
http://piscanner.com
and here is the distorted version received from si-list:
On âWednesdayâ, âJulyâ â31â, â2019â
â09â:â06â:â30â âAMâ âPDT, Cosmin Iorga
<dmarc-noreply@xxxxxxxxxxxxx> wrote:
s flow through the metallic chassis and why, and then use the fundamental laws
to make sure that the chassis currents cannot couple into your system. For
example, if you connect the chassis to your system ground with only one wire
(one connection point) can the chassis currents flow into your system? Start
from this and you will find the answer and more than that - you will understand
the fundamental Physics mechanisms involved in your
structure.Regards,Cosminhttp://piscanner.com
Â
  On âWednesdayâ, âJulyâ â31â, â2019â
â06â:â27â:â11â âAMâ âPDT, LD <dmarc-noreply@xxxxxxxxxxxxx>
wrote:Â
I recently came out of a review where the designers had placed chassis ground
on the pwb on the second layer. I tried to advise against it but was quickly
shot down. I would like some help explaining why this is an issue and possibly
an approach to show them in analysis or simulation.
The stackup is from top to bottom is
signalchasis gndgnd (or power)signal
gndpowergnd
signal
gnd
... same down
high speed signals come in on connectors they are all differential. The highest
data rate is 1.2 Gpbs cml and the lowest are around 40mbps RS422. There is also
lvds signaling. All the ICs are tied to power and gnd. Chassis ground is not
directly connected to signal ground other than through inter layer board
capacitance. They have done this on both sides of the boards. The designer is
claiming it is better for EMI.
Please if someone can help prove my case that this is the wrong thing to do, or
if someone can correct my thinking and show me why this is OK please respond
with an thorough explanation and possible ways to simulate this or analyze it.Â
Leonard Dieguez
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Â
Â
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      http://www.qsl.net/wb6tpu
Â
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//www.freelists.org/webpage/si-list
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