I recently came out of a review where the designers had placed chassis ground
on the pwb on the second layer. I tried to advise against it but was quickly
shot down. I would like some help explaining why this is an issue and possibly
an approach to show them in analysis or simulation.
The stackup is from top to bottom is
signalchasis gndgnd (or power)signal
gndpowergnd
signal
gnd
... same down
high speed signals come in on connectors they are all differential. The highest
data rate is 1.2 Gpbs cml and the lowest are around 40mbps RS422. There is also
lvds signaling. All the ICs are tied to power and gnd. Chassis ground is not
directly connected to signal ground other than through inter layer board
capacitance. They have done this on both sides of the boards. The designer is
claiming it is better for EMI.
Please if someone can help prove my case that this is the wrong thing to do, or
if someone can correct my thinking and show me why this is OK please respond
with an thorough explanation and possible ways to simulate this or analyze it.Â
Leonard Dieguez
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