Hi Seow,
Thank you very much for your patient reply. If I have other concerns, I
will contact with you again~
Regards
On Sat, Dec 19, 2015 at 4:09 AM, Hock Seow <hseow@xxxxxxxxx> wrote:
Hi Jun,
There is no short cut. Good SI Engineer would speed long hours in the
lab performing measurement and try to understand their SerDes deviation,
Channel deviation and what causes the different between measured and model.
Some deviations might be PCB vendors manufacturing process related, some
might be measurement setup related, some might be the accuracy of the
models. The more you doing it, the better you will be. All the SI Experts
in the list spent countless hours in the labs, with excellent hand-on
experience. You are on the right track.
You might find the following steps helpful:
- Understand the limitation of your SerDes. Include the Tx Jitter, Rx
min Noise Floor, min/max channel length that the SerDes could successfully
operate at room temp or better, over different temperature and voltage
effects. Even better if you have corner lot of the SerDes to understand the
Process deviation
- Minimize all possible interference sources in your systems/channels,
including:
- Reflections: Most reflection are caused by signal transition.
Like Layers transition (Via), into and out of interconnect, AC Coupling cap
- Crosstalk: Most Crosstalk are layout related (Routing layer,
distance between week victim and strong aggressors, pin assignment on
interconnect)
- Noise Floor: Most Tx/Rx internal Jitter are related to
Digital/Analog Power Isolation, Supply Noise. (PI help here)
- Once you know the min/max channel capability of the SerDes, design
your channel so that the final channel is within the min/max range (not be
too close to the min or max). The channel that is within the Min/Max range
imply that the SerDes's internal Tx/Rx EQ are away from their saturation
working range and this provide margin for the SerDes's Tx/Rx internal EQ to
train and find the best setting to equalize the channel over PVT
The two major suppliers for SAS 12Gbps support Training in their hardware
and model. Just a warning, model are not always accurate. Expect at least
5% and typically, more than 10% different between hardware and model.
Accurate model implying that the SerDes Vendors have to put many
designers in the model development, which I do not see this happening. By
the way, the only repeater that is transparent to the Tx/Rx Training and
also allow user to capture end-to-end channel model is Linear Equalizer.
Happy Holidays!
Regards
Hock
------------------------------
*From:* jun zhang <zhangjun5960@xxxxxxxxx>
*To:* Hock Seow <hseow@xxxxxxxxx>; "si-list@xxxxxxxxxxxxx" <
si-list@xxxxxxxxxxxxx>
*Sent:* Wednesday, December 16, 2015 4:38 AM
*Subject:* [SI-LIST] Re: redriver issue
Hi Hock,
Thank you very much.
For correlation between simulation and measurement. I also approach some
questions.
For transient simulation, 100,0000 bits will run for tedious time. If I set
bits more, the tools will reports errors. However in measurement, it's easy
to catch 1e9 bits on scope. Because the number of bits sent in simulation
and measurement are on different order, it's difficult to correlate them
such as eye diagram, bath curves and so on.
Second, for some types of Serdes, there is training process which will give
optimized equalization combinations. Sometimes we can't read out the eq
such as from SSD. However, in simulation there is no training process and
equalization is set by ourselves.
Thirdly, simulation can't reveal the device behavior such as in different
PVT cases, TX jitter.
do you have any good suggestions to overcome the above difficulties?
Hope to your reply
Regards
On Wed, Dec 16, 2015 at 5:25 AM, Hock Seow <hseow@xxxxxxxxx> wrote:
Hi Jun,loss.The
I do not find any usefulness when the vendor provide pre/post channel
reflection, crosstalk all would degrade the channel and will show up inrepeater,
your Insertion Loss plot. Return Loss capture the reflection effect too.
Lab measurement and simulation are needed to ensure you have sufficient
system margin.
Anytime when the repeater is non-linear, the pre and post channel are
independent from each other, with the exception of Limiting type
where the non-equalized jitter would get lock into the output signal. Init
simple term, Tx Emphasis and Rx input EQ help to reduce the channel ISI.
You should always go with a well design Linear Equalizer if you need to
support various data rate, different ac coupling interfaces and different
data modulations. Only a well design Linear Equalizer allow you include
into your system channel to capture your end-to-end channel using a VNA.different
Just note that not all repeater are build the same. For example, the CDR
have different loop bandwidth, the DFE have different tap weight,
algorithm, different Linear Equalizer have different Linearity and Gain
profiles. etc. You have to do your research.
Thanks!
Hock
------------------------------
*From:* jun zhang <zhangjun5960@xxxxxxxxx>
*To:* "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
*Sent:* Tuesday, December 15, 2015 4:50 AM
*Subject:* [SI-LIST] Re: redriver issue
However,
Hi experts,
Sometimes redriver vendors will generously give us spreadsheet about
pre-channel insertion loss and post-channel redrivers can handle.
in real channel, there are crosstalk, discontiuities. Do they notinfulence
much compared with insertion loss?the
Regards
On Tue, Dec 15, 2015 at 4:28 AM, Hock Seow <dmarc-noreply@xxxxxxxxxxxxx>
wrote:
Hi All,this
The new, well written Intel white paper (Rev 1.2, Oct 2015) compare
different repeats in market, would provide more useful information on
topic. Go to Intel site and search for "repeater" and the white paper
should be the first one in the search result. Thanks!
Hock
From: Vinu Arumugham <dmarc-noreply@xxxxxxxxxxxxx>
To: si-list@xxxxxxxxxxxxx
Sent: Monday, December 14, 2015 10:23 AM
Subject: [SI-LIST] Re: redriver issue
A retimer "resets" the jitter. So every segment of the link can have
thenfull interconnect jitter budget.strange
However, the wander budget is NOT reset. Wander being defined as low
frequency jitter that is tracked by the CDR.
So wander introduced by the retimer needs to be accounted in the
end-to-end wander budget.
Industry standards may not always specify the details of wander
budgeting for retimer based links.
This increases the risk of interoperability failures.
Simple retimers are usually protocol agnostic. So things like link
training, receiver detection may not work.
Thanks,
Vinu
On 12/12/15 19:01, jun zhang wrote:
Dear all,
I focus on redriver now which amplifies the signal. I have tried both
linear and nonlinear redrivers in our projects and approach some
returnissues.
Besides above questions, I also have interest in the influence of
andloss, crosstalk, TX jitter, RX jitter to the performance of redriver
wrote:the correlation between simulation and measurement.
Hope to your reply.
Regards
On Sat, Dec 12, 2015 at 11:15 PM, Walter Katz <wkatz@xxxxxxxxxx>
and
Chuck,
Correct. In the IBIS standard we use three terms, Repeater, Redriver
si-list-bounce@xxxxxxxxxxxxxthenRetimer.
A Repeater is either a Redriver or a Retimer. A Retimer recovers and
regenerates the signal. A Redriver amplifies the signal, and this
amplification can either be linear, or nonlinear.
Walter
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:
]
On
Behalf Of Chuck Corley
Sent: Saturday, December 12, 2015 10:04 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: redriver issue
Hi Jun;
For your discussion there are several types of devices. There are
"redrivers" which primarily rebuffer signals for amplititude, and
reducenamesthere
are also "retimers" which recover and regenerate the signals. The
for
these functions can vary between manufacturers.
Chuck
Chuck Corley
National Instruments
On 2015-12-12 03:27, jun zhang wrote:
Hi all,
I think redriver is an old and still difficult topic.
we approach in simulation, redriver can amplify amplitude but
can'ttiming margin case.
Also in test, we approach the case when adding in redriver, TX
itfind RX.
In redriver chip side, there are different kinds of redrivers:
limiting redriver and linear redriver.
It also seems the effects of redrivers are sensitive to positions
islocates, expecially for limiting redriver.
We may ship products that can work for PCIE Gen2 but fail for Gen3.
Because
of shipment already, we can't add redrivers in our products. So it
products.an awkard situation when we want to run higher speed on our
first
So I hope you can share some successful experiecnes on this topic.
When we judge that the insertion loss of the link is high, the
fieldaddingthought is adding redriver. But do we need to think more before
fieldredrivers?
Are
we afraid that adding redriver will give even worse effects? What
kinds of redrivers are most suitable to our link?
Hope to your discussion on this interesting topic
--
best wishes,
Jun Zhang
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