[SI-LIST] Re: random pulse generation in SPICE
- From: Anto Davis <antokdavis@xxxxxxxxx>
- To: Romi Mayder <romi.mayder@xxxxxxxxxx>
- Date: Mon, 5 Jan 2015 15:47:52 +0530
Thanks Romi,
Anto
On Sun, Jan 4, 2015 at 11:47 PM, Romi Mayder <romi.mayder@xxxxxxxxxx> wrote:
> Hi Ando,
>
> You can model the silicon behavior using Power-Aware IBISv5.0 models which
> support BIRDS 95/98. Then, connect your PDN model to the pull-up/power
> clamp node of the IBISv5.0 models.
>
> If using S-parameter models including both signal nets and power nets, use
> per-port reference impedances which is supported by Touchstone v2.0.
>
> A representative example of Power-Aware IBISv5.0 models can be found here:
>
> <http://www.xilinx.com/member/ultrascale_select_io_ibis/>
>
> A DesignCon2013 paper highlighting the advantages of using Power Aware
> IBISv5.0 models over encrypted transistor-level netlists can be found here:
>
>
> https://www.cadence.com/rl/Resources/conference_papers/4-WA1_Paper_Using%20Power%20Aware%20IBIS%20v5.0%20Behavioral%20IO%20Models.pdf
>
> I hope this helps answer your question.
>
>
>
> Romi
>
>
> -----Original Message-----
> From: Anto Davis [mailto:antokdavis@xxxxxxxxx]
> Sent: Saturday, January 03, 2015 09:23 PM Pacific Standard Time
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] random pulse generation in SPICE
>
> Hi,
> I have a PDN with some number of capacitors.
> I want to study the PDN voltage, when the switching current is varying as
> in a real IC.
> What are the methods to study the effect.
>
> Anto
>
>
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