[SI-LIST] Re: measuring Hi-Z and Lo-Z state
- From: "Ingraham, Andrew" <Andrew.Ingraham@xxxxxxxxxx>
- To: "'si-list@xxxxxxxxxxxxx'" <si-list@xxxxxxxxxxxxx>
- Date: Fri, 15 Jun 2001 08:31:26 -0400
> I am running hspice simulation on a bidirectional IO buffer provided by
> my vendor. I am wondering whether there is a standard circuit
> configuration to measure the Hi-Z and the Lo-Z state of the buffer? I
> want to make sure that bus contention does not happen for this
> interface.
What do you want to measure? Ioff? Ton and Toff?
Most logic databooks (Fairchild, Moto, Philips, TI, etc.) have examples of
test circuits for measuring their chips, which is one way to start. Check
your IC vendor's databook. For timing (Ton and Toff), a popular test load
is a resistance to GND or to Vdd or Vdd/2 (or some other voltage), in
parallel with a small capacitance, and measuring when the voltage crosses
some value. However, test circuits depend on the logic family and/or
vendor, and differences between them would be reflected in the data sheet
timing values.
In lieu of vendor-specified test circuits and AC specs, there are various
ways you can check for bus contention. Simulate the bus, set up your
worst-case skews, and monitor the output currents, for example. See if the
currents increase or overlap as you adjust the skew.
Andy
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