[SI-LIST] Re: layout of DSP driving 2 SDRAM
- From: "Tang, Linda [Xin Cai]" <LindaXinCai.Tang@xxxxxxxxxx>
- To: Ihsan Erdin <erdinih@xxxxxxxxx>
- Date: Mon, 17 Sep 2012 19:54:32 -0500
Hi Ihsan,
First thank you very much.
You said the length adjustment of those signal tracks is the most important
part of the design.
Does that mean address traces length are same as clock trace length,
for data trace, every byte traces have same length (of course there is
tolerance).
I don't have any SI analyzer tool, so I will do it as this way.
Best regards,
Linda
From: Ihsan Erdin [mailto:erdinih@xxxxxxxxx]
Sent: Friday, September 14, 2012 6:55 PM
To: Tang, Linda [Xin Cai]
Cc: si-list@xxxxxxxxxxxxx
Subject: Re: [SI-LIST] layout of DSP driving 2 SDRAM
Linda,
From your description, I understand a source synchronous (and single data rate)
SDRAM interface with a bit time of approximately 6ns. That is, you'll have to
meet the setup/hold time requirements within 6ns including the signal
propagation time on the lines. Depending on the timing specs of the DSP, you'll
most probably have to route the clock and address/data signals with adequate
skew in order to meet the timing requirements. Thus, the length adjustment of
those signal tracks is the most important part of the design.
As for the star vs. daisy-chain configuration, I would recommend the latter. It
is true it will cause a ledge on the signal edges of the device closer to the
controller, depending on the stub length but if the margins are good enough and
with proper routing that will usually be acceptable. Another option is to
consider clamshell memory devices (if available) that go both sides of the
card. That will practically eliminate the stub and solve the headache
concerning the placement of series resistors close to the memory devices (for
the data signals.) The downside of this configuration is that you may not probe
the signals at the memory pins in the lab.
Whatever your choice is this is a case where some circuit simulation effort
will be a smart investment for the design.
Regards,
Ihsan
On Wed, Sep 12, 2012 at 1:33 AM, Tang, Linda [Xin Cai]
<LindaXinCai.Tang@xxxxxxxxxx<mailto:LindaXinCai.Tang@xxxxxxxxxx>> wrote:
Hi ALL,
I have some queries about SDRAM layout.
One DSP drives two SDRAM,
The clock frequency is 166MHz.
The clock pulse width generated by DSP is 3 ns.
But I can't find the 10~90 rise time.
There are series resistors between DSP and SDRAM.
Now the series resistors are close to driver,
that means, the series resistors for data signals can be close to DSP or SDRAM,
All other series resistors only can close to DSP.
There are two methods.
One is tee topology.
The trace length from Rs to SDRAM1 equals to the trace length from Rs to SDRAM2.
In this topology, Rs+Rdrive=Z0. To remain trace impedance equals Z0, the trace
width of bifurcated line need to be 1/2w (if the trace width is w from DSP to
Rs).
I think it is difficult to control trace impedance, since impedance change is
too much.
In this topology, the series resistor only useful for slow down the 10~90 rise
or fall time of the signal, that also can
decrease EMI.
In my opinion, maybe we can add one buffer between Rs and SDRAM to make tee
topology work. Between buffer and SDRAM, there is series resistor.
The other is daisy chain.
The signal travels from DSP to Rs, then to SDRAM1, last to SDRAM2.make the
Rs+Rdrive=Z0, and make the stub trace length to SDRAM as short as possible. The
maximum length of stub trace is less than 1/5*(electrically long trace).
Every one, your any comment is welcome.
Thanks and best regards,
Linda Tang
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