[SI-LIST] Re: jitter on differential pairs
- From: christopher furman <chris_furman@xxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Tue, 12 Aug 2003 11:01:43 -0700 (PDT)
Well,
PLLs are pretty cheap these days. I'd try and keep
eveything on the daughter board; better control of the
environment affecting the PLL.
--- Denis Downey <denisd@xxxxxxxx> wrote:
> I'm running ADCs at 163MHz. The ADC clock jitter
> spec for my application is
> 3ps and the ADCs need differential clock drive
> (PECL)
>
> The ADcs are on daughter cards and I'm wondering if
> I can generate the
> clocks for all three daughter boards on the base
> board, and just distribute
> the clock through a connector to each daughter card.
>
> The alternative is to put a separate PLL on each
> daughter card.
>
> If I use the central generation approach, then
> obviously, the differential
> tracking must be closely matched, but are there
> other issues ?
>
> In particular, will the clock jitter increase as I
> increase the separation
> between the clock source and termination at this
> frequency ?
>
> I've seen several references to an increase in clock
> jitter with trace
> length on 5GHz and 10GHz differential tracking,
> which I'm assuming is
> related to attenuation at these frequencies.
>
> Does anyone have any experience regarding negative
> impact on clock jitter
> over (say) 6 inches of differential pair (FR4) plus
> a controlled impedance
> connector ?
>
> Thanks !
>
>
>
> Denis Downey
> Com21 European Development Center
> Airport Business Park, Cork Ireland
> +353 21 7305814
>
>
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