[SI-LIST] issue in IBIS modelling of LVDS buffer
- From: <chandrasekaran.nithya@xxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Thu, 26 Aug 2004 09:08:54 +0530
.
Hi,
Iam facing a problem in IBIS modelling of a non-terminated LVDS
buffer.
Actually the spec indicates that for proper functioning a terminated
resistor of 100ohms is to be connected between pad and padn.
Hence this led me to conclude that the buffer is a non-terminated one.
my doubt is
1.whether we need to connect the 100ohm resistor between pad and padn
for generating the ibis model?
Also we tried both - connecting the resistor and without connecting the
resistor while ibis model generation.
2.The ibis generated VT waveforms are not matching with the spice
waveform in verification(spice vs hspice (used IBIS model in
hspice)).The voltage levels itself are not matching in both the cases. A
difference of about (1.0-1.2)V. Hence not able to figure out what
exactly causes the mismatch.
3.Please can anyone clarify as to what setup I should give in case of VI
and VT waveforms for generating and verifying IBIS file for LVDS
buffer(terminated and non-terminated).It would be more helpful if anyone
could give the setup in diagramatic form which will ensure accurate
modelling.Also if possible could anyone think on a generic sense and
tell us what might be the possible causes for the mismatch.
regards
salainithya
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