Couple of things on LVDS: 1) My experience is that LVDS spice models cannot be measured or work correctly single ended. They are relying on current steering and the path must be complete. 2) LVDS is spec'd with a current source that seems to often be implemented with a large series capacitor between VCC and the output gate. This means that different current will be supplied at different frequencies (there is a resistor shunt for DC). This cannot be modeled with completely correctly with 3.X ibis models. You end up with frequency dependent models. I wrote an article on this for PCD once but I don't know if they keep around copies on the web. take care, jon -----Original Message----- From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Muranyi, Arpad Sent: Thursday, August 26, 2004 9:44 AM To: si-list@xxxxxxxxxxxxx Subject: [SI-LIST] Re: issue in IBIS modelling of LVDS buffer Salainithya, Look at the presentation(s) on modeling differential buffers if you haven't done so yet: http://www.eda.org/pub/ibis/summits/oct03/muranyi.pdf Arpad Muranyi Intel Corporation =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 -----Original Message----- From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of chandrasekaran.nithya@xxxxxxxxx Sent: Wednesday, August 25, 2004 8:39 PM To: si-list@xxxxxxxxxxxxx Subject: [SI-LIST] issue in IBIS modelling of LVDS buffer . Hi, Iam facing a problem in IBIS modelling of a non-terminated LVDS buffer. Actually the spec indicates that for proper functioning a terminated resistor of 100ohms is to be connected between pad and padn. Hence this led me to conclude that the buffer is a non-terminated one. my doubt is 1.whether we need to connect the 100ohm resistor between pad and padn for generating the ibis model? Also we tried both - connecting the resistor and without connecting the resistor while ibis model generation. 2.The ibis generated VT waveforms are not matching with the spice waveform in verification(spice vs hspice (used IBIS model in hspice)).The voltage levels itself are not matching in both the cases. A difference of about (1.0-1.2)V. Hence not able to figure out what exactly causes the mismatch. 3.Please can anyone clarify as to what setup I should give in case of VI and VT waveforms for generating and verifying IBIS file for LVDS buffer(terminated and non-terminated).It would be more helpful if anyone could give the setup in diagramatic form which will ensure accurate modelling.Also if possible could anyone think on a generic sense and tell us what might be the possible causes for the mismatch. regards salainithya Confidentiality Notice The information contained in this electronic message and any attachments to this message are intended for the exclusive use of the addressee(s) and may contain confidential or privileged information. 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