Beware of unvalidated simulations. They often lead you to incorrect
conclusions.
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of jun zhang
Sent: Thursday, December 24, 2015 8:35 PM
To: Orin Laney <olaney@xxxxxxxxx>; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: ground recessing
Hi Laney,
Happy Christmas!
My AC cap is located on top layer, GND layer 2 has some ground recessing and
the next ground layer is GND layer 4. From my simulation yesterday, I find
that the electric field transform from between the trace and G02 to between
the pad of the cap and G04 suddenly.
I want to know without GND vias to conductor the electric field smoothly,
what bad effects this sudden transform (G02->G04) will happen? Does emi will
become bad? Does crosstalk will become serious?
Anyway I think this sudden transform is bad for return path. But I still
want to know the badness quantitatively.
Hope to your reply
Regards
On Thu, Dec 24, 2015 at 1:40 PM, jun zhang <zhangjun5960@xxxxxxxxx> wrote:
Hi Laney,
Thank you very much for your suggestions. Indeed there are large
amounts of return currents in the gnd plane from some text books.
Regards
On Thu, Dec 24, 2015 at 1:31 PM, Orin Laney <olaney@xxxxxxxxx> wrote:
Total return currents in a diff pair sum to zero but they are not
individually zero and still need a local return path. You should use
eight individual slots rather than one big one. The foil straps
between slots let return currents stay local to the pair.
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]
On
Behalf Of jun zhang
Sent: Wednesday, December 23, 2015 9:01 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] ground recessing
Hi experts,
I approach a case about ground recessing. For eight PCIE lanes, the
sixteen AC caps are in parrell to each other. I want to do ground
recessing underneath the caps and therefore the ground recessing
becomes a long slot under sixteen caps.
Although from simulation, the TDR curves are good. However, do you
worry that the signal traces in the eight lanes (especially in the
middle) will not find minimal loop return currents?
Besides TDR, what parameters should I also watch in HFSS for such a case?
crosstalk? EMI parameters?
Regards
--
best wishes,
Jun Zhang
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best wishes,
Jun Zhang
