What impedance dip? You can't even see that. As always, don't do something
like this on speculation.
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Orin Laney
Sent: Thursday, December 24, 2015 2:11 PM
To: 'Lee Ritchey' <leeritchey@xxxxxxxxxxxxx>; zhangjun5960@xxxxxxxxx;
si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: ground recessing
So true if proper design practices are followed. What happens is the heresy
of, say, using an 0603 capacitor on a .008" trace, and then using the heresy
of compensating for the impedance dip caused by the ~.040 pad width with a
ground cutaway. Better they should use traces and caps of the same or nearly
equal width over a ground plane of proper distance, but in a cram-it-in
world whatya gonna do? So, we smile and keep passing out the SI consulting
business cards...
Orin
-----Original Message-----
From: Lee Ritchey [mailto:leeritchey@xxxxxxxxxxxxx]
Sent: Thursday, December 24, 2015 12:00 PM
To: zhangjun5960@xxxxxxxxx; 'Orin Laney'; si-list@xxxxxxxxxxxxx
Subject: RE: [SI-LIST] Re: ground recessing
Ground recessing is not required, so don't do it. We have built test PCBs
with and without ground recessing and found that there is little change.
What change there is results in more loos at high frequencies when you
remove the ground from under that AC capacitor mounting pads.
I wonder who came up with this rule. Whoever did, did not do any validation
of its worth.
We have entirely too much of this in application notes.
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of jun zhang
Sent: Wednesday, December 23, 2015 9:40 PM
To: Orin Laney <olaney@xxxxxxxxx>; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: ground recessing
Hi Laney,
Thank you very much for your suggestions. Indeed there are large amounts of
return currents in the gnd plane from some text books.
Regards
On Thu, Dec 24, 2015 at 1:31 PM, Orin Laney <olaney@xxxxxxxxx> wrote:
Total return currents in a diff pair sum to zero but they are not
individually zero and still need a local return path. You should use
eight individual slots rather than one big one. The foil straps
between slots let return currents stay local to the pair.
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]
On
Behalf Of jun zhang
Sent: Wednesday, December 23, 2015 9:01 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] ground recessing
Hi experts,
I approach a case about ground recessing. For eight PCIE lanes, the
sixteen AC caps are in parrell to each other. I want to do ground
recessing underneath the caps and therefore the ground recessing
becomes a long slot under sixteen caps.
Although from simulation, the TDR curves are good. However, do you
worry that the signal traces in the eight lanes (especially in the
middle) will not find minimal loop return currents?
Besides TDR, what parameters should I also watch in HFSS for such a case?
crosstalk? EMI parameters?
Regards
--
best wishes,
Jun Zhang
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