[SI-LIST] effect of ref clock's phase and Frequnecy on SERDES operation
- From: prasad <hariprasad.palli@xxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Fri, 9 Sep 2011 01:56:41 +0530
Hi everyone,
i need your help in understanding effect of ref clock on serdes operation.
I am trying to understand one design, where IBM's 6.4Gbps serdes was used.
I went through its architecture, and i could see that the same ref clock is
being used for Rx and Tx.
i would like to understand the effect of frequency variation and Phase
variation of the reference clock provided on both Tx side and Rx side.
I assume on RX side, there might be dependancy on the frequnecy but not
phase, where as on Tx side, there would be dependancy on both phase and
frequency. Please correct if i have mistaken.
It would help , even if you point to good source of document related to this
SERDES and CDRs.
Thank you everyone in advance....
Regards,
prasad
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