[SI-LIST] Re: effect of ref clock's phase and Frequnecy on SERDES operation

  • From: Vinu Arumugham <vinu@xxxxxxxxx>
  • To: prasad <hariprasad.palli@xxxxxxxxx>
  • Date: Fri, 09 Sep 2011 11:08:28 -0700

Prasad,
For a serdes reference clock, phase jitter, phase wander and stability 
are factors to consider.

Phase jitter is defined in JESD65B


      JEDEC STANDARD
      
<http://www.google.com/url?sa=t&source=web&cd=1&ved=0CBYQFjAA&url=http%3A%2F%2Fwww.jedec.org%2Fsites%2Fdefault%2Ffiles%2Fdocs%2Fjesd65b.pdf&rct=j&q=JESD65B&ei=PURqToqxA6vSiAK15sGwDg&usg=AFQjCNEvtgtr3n428b1trmc9x1H7KJ_LpA>

Phase wander uses the same definition. Usually, phase jitter refers to 
jitter frequency components above FBaud/1667 and phase wander refers to 
frequency components below FBaud/1667.

Stability specifies the maximum offset of the clock frequency from the 
nominal value in ppm. If the RX and TX clocks are from the same source, 
the RX to TX ppm offset is 0.  Usually serdes are designed to accept an 
RX to TX ppm offset of at least 200ppm.

Reference clock phase jitter and wander are filtered by the serdes PLL 
and the CDR. Therefore only the residual jitter/wander affect the signal 
eye observed at the RX sampler and impact performance. Serdes PLLs 
usually have low pass transfer characteristics with a corner frequency 
of ~FBaud/1000 and a 20dB/decade roll-off. CDRs usually have high pass 
transfer characteristics with a corner frequency of ~FBaud/1667 and a 
20dB/decade roll-off.

Thanks,
Vinu

prasad wrote:
> Hi everyone,
> i need your help in understanding effect of ref clock on serdes operation.
>
> I am trying to understand one design, where IBM's 6.4Gbps serdes was used.
> I went through its architecture, and i could see that the same ref clock is
> being used for Rx and Tx.
>
> i would like to understand the effect of frequency variation and Phase
> variation of the reference clock provided on both Tx side and Rx side.
>
> I assume on RX side, there might be dependancy on the frequnecy but not
> phase, where as on Tx side, there would be dependancy on both phase and
> frequency. Please correct if i have mistaken.
>
> It would help , even if you point to good source of document related to this
> SERDES and CDRs.
>
>
> Thank you everyone in advance....
>
>
> Regards,
> prasad
>
>
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