I'm designing 6Gbps interconnect using edge connector.
i try to optimize it's layout using this flow
1. Layout edit and extraction in PowerSI ( up to 35GHz)
2. ADS TDR simulation and s parameter viewer S11 analysys
3. if interconnect is 100 +-5R stop
4. go to 1
i have few questions :
1. i use powersi because of fast extraction time . do i need to use full
wave field solver for it? (cadence 3DFEM). in my setup i cut traces to be
very short , so only pads of edge connector are extracted.
2. in tdr setup i can use any step rise time, i found that 10ps works well.
but actual rise time in the system will be 75-80ps. do i need something
more close to real impedance?
results are pretty different?
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