[SI-LIST] AW: edge connector layout optimization

  • From: "Havermann, Gert" <Gert.Havermann@xxxxxxxxxxx>
  • To: "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
  • Date: Tue, 18 Aug 2015 09:48:12 +0000

short traces are bad for optimization process. The section that will be
optimized should be connected with impedance controlled traces of at least 5
times the electrical length of the section under test, and should contain no
other impedance discontinuity. You don't want multiple reflections to mask your
optimization.
If PowerSI can be used depends on the geometry of the interconnect. The edge
connector will have a lead in zone at the contact tip to allow mating. this
will act as a stub when the contact is fully mated. If PowerSI lets you model
this stub, and the contact thickness (as added copperweight) and the inductive
nature of the contact along with the coupling to neighboring contacts, then
PowerSI may work for you. If not, then you need a 3D tool. This is especially
true if you try to match the impedance by adding cutouts in the GND plane
underneath the traces.
10ps risetime gives a higher resolution than 80ps and for optimization
prozesses that’s fine. The resolution should be the only difference between
both TDR plots. If there are other differences, then the tool might not be
appropriate, or there are other effects in place (Multiple refelctions?).

BR
Gert


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-----Ursprüngliche Nachricht-----
Von: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] Im
Auftrag von qantrix
Gesendet: Dienstag, 18. August 2015 09:35
An: si-list@xxxxxxxxxxxxx
Betreff: [SI-LIST] edge connector layout optimization

I'm designing 6Gbps interconnect using edge connector.
i try to optimize it's layout using this flow 1. Layout edit and extraction in
PowerSI ( up to 35GHz) 2. ADS TDR simulation and s parameter viewer S11
analysys 3. if interconnect is 100 +-5R stop 4. go to 1

i have few questions :
1. i use powersi because of fast extraction time . do i need to use full wave
field solver for it? (cadence 3DFEM). in my setup i cut traces to be very short
, so only pads of edge connector are extracted.
2. in tdr setup i can use any step rise time, i found that 10ps works well.
but actual rise time in the system will be 75-80ps. do i need something more
close to real impedance?
results are pretty different?


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Other related posts:

  • » [SI-LIST] AW: edge connector layout optimization - Havermann, Gert