[SI-LIST] Re: clock divider
- From: "Ingraham, Andrew" <a.ingraham@xxxxxxxx>
- To: <atokuz@xxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Thu, 27 Nov 2003 09:32:10 -0500
> I am looking for a solution which guarantees that (b)
> is always the case.
Then what you need is a rising-edge-triggered flip-flop.
Flip-flops are triggered by either the rising edge or the falling edge of
the input clock. Use the rising edge triggered variety (which happens to be
far more common).
By the way, the edges will not be perfectly aligned. There is a little
delay through the flip-flop, which causes the flip-flop's outputs ... (b)
and an inverted version of (b) ... to be a little delayed from the input
edges.
If that delay is undesirable, you could make a copy of the input clock so
that both it and the flip-flop's output are better aligned. Or, you could
do something like generate a 2X version of the input clock (with a delay and
an XOR), and use this with two more edge-triggered flip-flops to clock out
both signals at the same time.
Regards,
Andy
> /--------\ /---------\
> | | | |
> | | | |
> --------| |--------| |---------
>
>
> (a)
> |------------------|
> | |
> ------------------| |---------
>
>
> (b)
>
> |------------------|
> | |
> ---------| |-----------------
>
>
>
> I am looking for a solution which guarantees that (b)
> is always the case.
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