[SI-LIST] clock divider
- From: Ahmet Tokuz <atokuz@xxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Wed, 26 Nov 2003 15:03:20 -0800 (PST)
Hello,
I was wondering whether there's a way of dividing
clock by 2 deterministicly. I mean there may be two
outputs. However I am interested in the one with
where phase is synched. I mean both rising and falling
edges are aligned. Are there any way to ensure that?
thanks
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